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ARM: 8671/1: V7M: Preserve registers across switch from Thread to Handler mode
According to ARMv7 ARM, when exception is taken content of r0-r3, r12 is unknown (see ExceptionTaken() pseudocode). Even though existent implementations keep these register unchanged, preserve them to be in line with architecture. Reported-by: Dobromir Stefanov <dobromir.stefanov@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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@ -135,9 +135,11 @@ __v7m_setup_cont:
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dsb
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mov r6, lr @ save LR
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ldr sp, =init_thread_union + THREAD_START_SP
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stmia sp, {r0-r3, r12}
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cpsie i
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svc #0
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1: cpsid i
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ldmia sp, {r0-r3, r12}
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str r5, [r12, #11 * 4] @ restore the original SVC vector entry
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mov lr, r6 @ restore LR
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