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drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock() 

We want to differentiate between the DFP dotclock and TMDS clock
limits. Let's convert the current thing to just give us the
dotclock limit.

v2: Use Returns: for kdoc (Lyude)
    Fix up nouveau code too

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200904115354.25336-9-ville.syrjala@linux.intel.com
Reviewed-by: Lyude Paul <lyude@redhat.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2020-09-04 14:53:44 +03:00
parent 42f2562ca1
commit b770e84311
4 changed files with 23 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
drivers/gpu/drm/drm_dp_helper.c
View File

@ -616,41 +616,32 @@ int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
EXPORT_SYMBOL(drm_dp_read_downstream_info); EXPORT_SYMBOL(drm_dp_read_downstream_info);
/** /**
* drm_dp_downstream_max_clock() - extract branch device max * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
* pixel rate for legacy VGA
* converter or max TMDS clock
* rate for others
* @dpcd: DisplayPort configuration data * @dpcd: DisplayPort configuration data
* @port_cap: port capabilities * @port_cap: port capabilities
* *
* See also: * Returns: Downstream facing port max dot clock in kHz on success,
* drm_dp_read_downstream_info() * or 0 if max clock not defined
* drm_dp_downstream_max_bpc()
*
* Returns: Max clock in kHz on success or 0 if max clock not defined
*/ */
int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]) const u8 port_cap[4])
{ {
int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; if (!drm_dp_is_branch(dpcd))
bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DETAILED_CAP_INFO_AVAILABLE;
if (!detailed_cap_info)
return 0; return 0;
switch (type) { if (dpcd[DP_DPCD_REV] < 0x11)
return 0;
switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
case DP_DS_PORT_TYPE_VGA: case DP_DS_PORT_TYPE_VGA:
return port_cap[1] * 8 * 1000; if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
case DP_DS_PORT_TYPE_DVI: return 0;
case DP_DS_PORT_TYPE_HDMI: return port_cap[1] * 8000;
case DP_DS_PORT_TYPE_DP_DUALMODE:
return port_cap[1] * 2500;
default: default:
return 0; return 0;
} }
} }
EXPORT_SYMBOL(drm_dp_downstream_max_clock); EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
/** /**
* drm_dp_downstream_max_bpc() - extract downstream facing port max * drm_dp_downstream_max_bpc() - extract downstream facing port max
@ -793,14 +784,9 @@ void drm_dp_downstream_debug(struct seq_file *m,
seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
if (detailed_cap_info) { if (detailed_cap_info) {
clk = drm_dp_downstream_max_clock(dpcd, port_cap); clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
if (clk > 0)
if (clk > 0) { seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
if (type == DP_DS_PORT_TYPE_VGA)
seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
else
seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
}
bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid); bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);

4
drivers/gpu/drm/i915/display/intel_dp.c
View File

@ -261,8 +261,8 @@ intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
if (type != DP_DS_PORT_TYPE_VGA) if (type != DP_DS_PORT_TYPE_VGA)
return max_dotclk; return max_dotclk;
ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, ds_max_dotclk = drm_dp_downstream_max_dotclock(intel_dp->dpcd,
intel_dp->downstream_ports); intel_dp->downstream_ports);
if (ds_max_dotclk != 0) if (ds_max_dotclk != 0)
max_dotclk = min(max_dotclk, ds_max_dotclk); max_dotclk = min(max_dotclk, ds_max_dotclk);

4
drivers/gpu/drm/nouveau/nouveau_dp.c
View File

@ -239,8 +239,8 @@ nv50_dp_mode_valid(struct drm_connector *connector,
return MODE_NO_INTERLACE; return MODE_NO_INTERLACE;
max_clock = outp->dp.link_nr * outp->dp.link_bw; max_clock = outp->dp.link_nr * outp->dp.link_bw;
ds_clock = drm_dp_downstream_max_clock(outp->dp.dpcd, ds_clock = drm_dp_downstream_max_dotclock(outp->dp.dpcd,
outp->dp.downstream_ports); outp->dp.downstream_ports);
if (ds_clock) if (ds_clock)
max_clock = min(max_clock, ds_clock); max_clock = min(max_clock, ds_clock);

4
include/drm/drm_dp_helper.h
View File

@ -1643,8 +1643,8 @@ bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4], const u8 port_cap[4],
const struct edid *edid); const struct edid *edid);
int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4]); const u8 port_cap[4]);
int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
const u8 port_cap[4], const u8 port_cap[4],
const struct edid *edid); const struct edid *edid);