mirror of https://gitee.com/openkylin/linux.git
PCI: rcar: Cleanup style and formatting
This patch just makes symbol and function name changes to avoid potential conflicts, along with minor formatting changes. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Phil Edworthy
Bjorn Helgaas
parent
2c3fd4c935
commit
b77188495d
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@ -105,7 +105,7 @@
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#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
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#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
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#define PCI_MAX_RESOURCES 4
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#define RCAR_PCI_MAX_RESOURCES 4
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#define MAX_NR_INBOUND_MAPS 6
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struct rcar_msi {
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@ -127,7 +127,7 @@ static inline struct rcar_msi *to_rcar_msi(struct msi_chip *chip)
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struct rcar_pcie {
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struct device *dev;
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void __iomem *base;
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struct resource res[PCI_MAX_RESOURCES];
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struct resource res[RCAR_PCI_MAX_RESOURCES];
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struct resource busn;
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int root_bus_nr;
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struct clk *clk;
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@ -140,36 +140,37 @@ static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
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return sys->private_data;
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}
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static void pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
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unsigned long reg)
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static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
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unsigned long reg)
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{
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writel(val, pcie->base + reg);
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}
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static unsigned long pci_read_reg(struct rcar_pcie *pcie, unsigned long reg)
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static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
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unsigned long reg)
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{
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return readl(pcie->base + reg);
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}
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enum {
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PCI_ACCESS_READ,
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PCI_ACCESS_WRITE,
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RCAR_PCI_ACCESS_READ,
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RCAR_PCI_ACCESS_WRITE,
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};
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static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
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{
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int shift = 8 * (where & 3);
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u32 val = pci_read_reg(pcie, where & ~3);
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u32 val = rcar_pci_read_reg(pcie, where & ~3);
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val &= ~(mask << shift);
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val |= data << shift;
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pci_write_reg(pcie, val, where & ~3);
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rcar_pci_write_reg(pcie, val, where & ~3);
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}
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static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
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{
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int shift = 8 * (where & 3);
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u32 val = pci_read_reg(pcie, where & ~3);
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u32 val = rcar_pci_read_reg(pcie, where & ~3);
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return val >> shift;
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}
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@ -205,14 +206,14 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
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if (dev != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (access_type == PCI_ACCESS_READ) {
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*data = pci_read_reg(pcie, PCICONF(index));
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if (access_type == RCAR_PCI_ACCESS_READ) {
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*data = rcar_pci_read_reg(pcie, PCICONF(index));
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} else {
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/* Keep an eye out for changes to the root bus number */
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if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
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pcie->root_bus_nr = *data & 0xff;
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pci_write_reg(pcie, *data, PCICONF(index));
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rcar_pci_write_reg(pcie, *data, PCICONF(index));
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}
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return PCIBIOS_SUCCESSFUL;
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@ -222,20 +223,20 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Clear errors */
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pci_write_reg(pcie, pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
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rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
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/* Set the PIO address */
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pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | PCIE_CONF_DEV(dev) |
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PCIE_CONF_FUNC(func) | reg, PCIECAR);
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rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
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PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
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/* Enable the configuration access */
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if (bus->parent->number == pcie->root_bus_nr)
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pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
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rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
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else
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pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
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rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
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/* Check for errors */
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if (pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
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if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Check for master and target aborts */
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@ -243,13 +244,13 @@ static int rcar_pcie_config_access(struct rcar_pcie *pcie,
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(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (access_type == PCI_ACCESS_READ)
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*data = pci_read_reg(pcie, PCIECDR);
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if (access_type == RCAR_PCI_ACCESS_READ)
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*data = rcar_pci_read_reg(pcie, PCIECDR);
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else
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pci_write_reg(pcie, *data, PCIECDR);
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rcar_pci_write_reg(pcie, *data, PCIECDR);
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/* Disable the configuration access */
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pci_write_reg(pcie, 0, PCIECCTLR);
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rcar_pci_write_reg(pcie, 0, PCIECCTLR);
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return PCIBIOS_SUCCESSFUL;
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}
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@ -260,7 +261,7 @@ static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
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struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
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int ret;
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ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
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ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
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bus, devfn, where, val);
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if (ret != PCIBIOS_SUCCESSFUL) {
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*val = 0xffffffff;
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@ -286,7 +287,7 @@ static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
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int shift, ret;
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u32 data;
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ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
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ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
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bus, devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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@ -305,7 +306,7 @@ static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
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} else
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data = val;
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ret = rcar_pcie_config_access(pcie, PCI_ACCESS_WRITE,
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ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
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bus, devfn, where, &data);
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return ret;
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@ -323,7 +324,7 @@ static void rcar_pcie_setup_window(int win, struct resource *res,
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resource_size_t size;
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u32 mask;
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pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
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rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
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/*
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* The PAMR mask is calculated in units of 128Bytes, which
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@ -331,17 +332,17 @@ static void rcar_pcie_setup_window(int win, struct resource *res,
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*/
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size = resource_size(res);
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mask = (roundup_pow_of_two(size) / SZ_128) - 1;
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pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
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rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
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pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
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pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
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rcar_pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
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rcar_pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
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/* First resource is for IO */
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mask = PAR_ENABLE;
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if (res->flags & IORESOURCE_IO)
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mask |= IO_SPACE;
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pci_write_reg(pcie, mask, PCIEPTCTLR(win));
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rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
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}
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static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
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@ -353,7 +354,7 @@ static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
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pcie->root_bus_nr = -1;
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/* Setup PCI resources */
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for (i = 0; i < PCI_MAX_RESOURCES; i++) {
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for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
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res = &pcie->res[i];
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if (!res->flags)
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@ -405,7 +406,7 @@ static int phy_wait_for_ack(struct rcar_pcie *pcie)
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unsigned int timeout = 100;
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while (timeout--) {
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if (pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
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if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
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return 0;
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udelay(100);
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@ -428,15 +429,15 @@ static void phy_write_reg(struct rcar_pcie *pcie,
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((addr & 0xff) << ADR_POS);
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/* Set write data */
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pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
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pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
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rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
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rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
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/* Ignore errors as they will be dealt with if the data link is down */
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phy_wait_for_ack(pcie);
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/* Clear command */
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pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
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pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
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rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
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rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
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/* Ignore errors as they will be dealt with if the data link is down */
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phy_wait_for_ack(pcie);
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@ -447,7 +448,7 @@ static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
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unsigned int timeout = 10;
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while (timeout--) {
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if ((pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
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if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
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return 0;
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msleep(5);
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@ -461,17 +462,17 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
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int err;
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/* Begin initialization */
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pci_write_reg(pcie, 0, PCIETCTLR);
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rcar_pci_write_reg(pcie, 0, PCIETCTLR);
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/* Set mode */
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pci_write_reg(pcie, 1, PCIEMSR);
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rcar_pci_write_reg(pcie, 1, PCIEMSR);
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/*
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* Initial header for port config space is type 1, set the device
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* class to match. Hardware takes care of propagating the IDSETR
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* settings, so there is no need to bother with a quirk.
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*/
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pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
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rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
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/*
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* Setup Secondary Bus Number & Subordinate Bus Number, even though
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@ -495,17 +496,17 @@ static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
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rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
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/* Set the completion timer timeout to the maximum 50ms. */
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rcar_rmw32(pcie, TLCTLR+1, 0x3f, 50);
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rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
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/* Terminate list of capabilities (Next Capability Offset=0) */
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rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
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/* Enable MSI */
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if (IS_ENABLED(CONFIG_PCI_MSI))
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pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
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rcar_pci_write_reg(pcie, 0x101f0000, PCIEMSITXR);
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/* Finish initialization - establish a PCI Express link */
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pci_write_reg(pcie, CFINIT, PCIETCTLR);
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rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
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/* This will timeout if we don't have a link. */
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err = rcar_pcie_wait_for_dl(pcie);
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@ -543,7 +544,7 @@ static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
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phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
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while (timeout--) {
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if (pci_read_reg(pcie, H1_PCIEPHYSR))
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if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
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return rcar_pcie_hw_init(pcie);
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msleep(5);
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@ -582,7 +583,7 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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struct rcar_msi *msi = &pcie->msi;
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unsigned long reg;
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reg = pci_read_reg(pcie, PCIEMSIFR);
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reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
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/* MSI & INTx share an interrupt - we only handle MSI here */
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if (!reg)
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@ -593,7 +594,7 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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unsigned int irq;
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/* clear the interrupt */
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pci_write_reg(pcie, 1 << index, PCIEMSIFR);
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rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
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irq = irq_find_mapping(msi->domain, index);
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if (irq) {
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@ -607,7 +608,7 @@ static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
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}
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/* see if there's any more pending in this vector */
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reg = pci_read_reg(pcie, PCIEMSIFR);
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reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
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}
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return IRQ_HANDLED;
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@ -634,8 +635,8 @@ static int rcar_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
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irq_set_msi_desc(irq, desc);
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msg.address_lo = pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
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msg.address_hi = pci_read_reg(pcie, PCIEMSIAUR);
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msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
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msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
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msg.data = hwirq;
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write_msi_msg(irq, &msg);
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@ -712,11 +713,11 @@ static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
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msi->pages = __get_free_pages(GFP_KERNEL, 0);
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base = virt_to_phys((void *)msi->pages);
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pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
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pci_write_reg(pcie, 0, PCIEMSIAUR);
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rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
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rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
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/* enable all MSI interrupts */
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pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
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rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
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return 0;
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@ -809,6 +810,7 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
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if (cpu_addr > 0) {
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unsigned long nr_zeros = __ffs64(cpu_addr);
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u64 alignment = 1ULL << nr_zeros;
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size = min(range->size, alignment);
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} else {
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size = range->size;
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@ -824,13 +826,13 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
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* Set up 64-bit inbound regions as the range parser doesn't
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* distinguish between 32 and 64-bit types.
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*/
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pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
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pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
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pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
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rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
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rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
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rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
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pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
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pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
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pci_write_reg(pcie, 0, PCIELAMR(idx+1));
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rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
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rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
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rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
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pci_addr += size;
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cpu_addr += size;
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@ -935,7 +937,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
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|||
of_pci_range_to_resource(&range, pdev->dev.of_node,
|
||||
&pcie->res[win++]);
|
||||
|
||||
if (win > PCI_MAX_RESOURCES)
|
||||
if (win > RCAR_PCI_MAX_RESOURCES)
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -965,7 +967,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
data = pci_read_reg(pcie, MACSR);
|
||||
data = rcar_pci_read_reg(pcie, MACSR);
|
||||
dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
|
||||
|
||||
rcar_pcie_enable(pcie);
|
||||
|
|
|
|||
Loading…
Reference in New Issue