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dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML
Convert the ingenic,pinctrl.txt doc file to ingenic,pinctrl.yaml. In the process, some compatible strings now require a fallback, as the corresponding SoCs are pin-compatible with their fallback variant. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200622113740.46450-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Paul Cercueil
Linus Walleij
parent
7203d3684e
commit
b77eab32c4
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Ingenic XBurst pin controller
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
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be used as GPIOs, multiplexed device functions are configured within the
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GPIO port configuration registers and it is typical to refer to pins using the
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naming scheme "PxN" where x is a character identifying the GPIO port with
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which the pin is associated and N is an integer from 0 to 31 identifying the
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pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
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PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
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contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
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jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
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Required properties:
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--------------------
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- compatible: One of:
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- "ingenic,jz4740-pinctrl"
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- "ingenic,jz4725b-pinctrl"
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- "ingenic,jz4760-pinctrl"
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- "ingenic,jz4760b-pinctrl"
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- "ingenic,jz4770-pinctrl"
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- "ingenic,jz4780-pinctrl"
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- "ingenic,x1000-pinctrl"
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- "ingenic,x1000e-pinctrl"
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- "ingenic,x1500-pinctrl"
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- "ingenic,x1830-pinctrl"
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- reg: Address range of the pinctrl registers.
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Required properties for sub-nodes (GPIO chips):
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-----------------------------------------------
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- compatible: Must contain one of:
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- "ingenic,jz4740-gpio"
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- "ingenic,jz4760-gpio"
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- "ingenic,jz4770-gpio"
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- "ingenic,jz4780-gpio"
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- "ingenic,x1000-gpio"
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- "ingenic,x1830-gpio"
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- reg: The GPIO bank number.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- interrupts: Interrupt specifier for the controllers interrupt.
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- #interrupt-cells: Should be 2. Refer to
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../interrupt-controller/interrupts.txt for more details.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
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cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
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GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
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- gpio-ranges: Range of pins managed by the GPIO controller. Refer to
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../gpio/gpio.txt for more details.
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Example:
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--------
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pinctrl: pin-controller@10010000 {
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compatible = "ingenic,jz4740-pinctrl";
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reg = <0x10010000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpa: gpio@0 {
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compatible = "ingenic,jz4740-gpio";
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reg = <0>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <28>;
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};
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};
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@ -0,0 +1,136 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Ingenic SoCs pin controller devicetree bindings
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description: >
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
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may be used as GPIOs, multiplexed device functions are configured within the
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GPIO port configuration registers and it is typical to refer to pins using the
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naming scheme "PxN" where x is a character identifying the GPIO port with
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which the pin is associated and N is an integer from 0 to 31 identifying the
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pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
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and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
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contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
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JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
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pins.
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maintainers:
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- Paul Cercueil <paul@crapouillou.net>
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properties:
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nodename:
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pattern: "^pinctrl@[0-9a-f]+$"
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compatible:
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oneOf:
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- enum:
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- ingenic,jz4740-pinctrl
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- ingenic,jz4725b-pinctrl
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- ingenic,jz4760-pinctrl
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- ingenic,jz4770-pinctrl
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- ingenic,jz4780-pinctrl
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- ingenic,x1000-pinctrl
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- ingenic,x1500-pinctrl
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- ingenic,x1830-pinctrl
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- items:
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- const: ingenic,jz4760b-pinctrl
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- const: ingenic,jz4760-pinctrl
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- items:
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- const: ingenic,x1000e-pinctrl
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- const: ingenic,x1000-pinctrl
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^gpio@[0-9]$":
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type: object
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properties:
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compatible:
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enum:
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- ingenic,jz4740-gpio
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- ingenic,jz4725b-gpio
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- ingenic,jz4760-gpio
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- ingenic,jz4770-gpio
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- ingenic,jz4780-gpio
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- ingenic,x1000-gpio
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- ingenic,x1500-gpio
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- ingenic,x1830-gpio
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reg:
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items:
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- description: The GPIO bank number
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gpio-controller: true
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"#gpio-cells":
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const: 2
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gpio-ranges:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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description:
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Refer to ../interrupt-controller/interrupts.txt for more details.
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- gpio-controller
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- "#gpio-cells"
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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additionalProperties: false
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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examples:
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- |
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pin-controller@10010000 {
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compatible = "ingenic,jz4770-pinctrl";
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reg = <0x10010000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio@0 {
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compatible = "ingenic,jz4770-gpio";
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reg = <0>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 32>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <17>;
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};
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};
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