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net: marvell: mvpp2: add mvpp2_is_xlg() helper 

Add a mvpp2_is_xlg() helper to identify whether the interface mode
should be using the XLGMAC rather than the GMAC.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King 2019-02-11 10:23:10 +00:00 committed by David S. Miller
parent 86e58135bc
commit b7d286f01b
1 changed files with 9 additions and 11 deletions
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20
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
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@ -965,6 +965,11 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
} }
/* Port configuration routines */ /* Port configuration routines */
static bool mvpp2_is_xlg(phy_interface_t interface)
{
return interface == PHY_INTERFACE_MODE_10GKR ||
interface == PHY_INTERFACE_MODE_XAUI;
}
static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
{ {
@ -1181,9 +1186,7 @@ static void mvpp2_port_enable(struct mvpp2_port *port)
u32 val; u32 val;
/* Only GOP port 0 has an XLG MAC */ /* Only GOP port 0 has an XLG MAC */
if (port->gop_id == 0 && if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
(port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
val = readl(port->base + MVPP22_XLG_CTRL0_REG); val = readl(port->base + MVPP22_XLG_CTRL0_REG);
val |= MVPP22_XLG_CTRL0_PORT_EN | val |= MVPP22_XLG_CTRL0_PORT_EN |
MVPP22_XLG_CTRL0_MAC_RESET_DIS; MVPP22_XLG_CTRL0_MAC_RESET_DIS;
@ -1202,9 +1205,7 @@ static void mvpp2_port_disable(struct mvpp2_port *port)
u32 val; u32 val;
/* Only GOP port 0 has an XLG MAC */ /* Only GOP port 0 has an XLG MAC */
if (port->gop_id == 0 && if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) {
(port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
val = readl(port->base + MVPP22_XLG_CTRL0_REG); val = readl(port->base + MVPP22_XLG_CTRL0_REG);
val &= ~MVPP22_XLG_CTRL0_PORT_EN; val &= ~MVPP22_XLG_CTRL0_PORT_EN;
writel(val, port->base + MVPP22_XLG_CTRL0_REG); writel(val, port->base + MVPP22_XLG_CTRL0_REG);
@ -3146,8 +3147,7 @@ static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
if (port->phy_interface == PHY_INTERFACE_MODE_XAUI || if (mvpp2_is_xlg(port->phy_interface))
port->phy_interface == PHY_INTERFACE_MODE_10GKR)
ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
else else
ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
@ -3155,9 +3155,7 @@ static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
} }
if (port->gop_id == 0 && if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface))
(port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
port->phy_interface == PHY_INTERFACE_MODE_10GKR))
mvpp2_xlg_max_rx_size_set(port); mvpp2_xlg_max_rx_size_set(port);
else else
mvpp2_gmac_max_rx_size_set(port); mvpp2_gmac_max_rx_size_set(port);