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Few late SoC changes for v5.5 merge window 

These changes just clean up few typos, and there is one non-critical
 correction of missing put_device() after calling of_platform_populate()
 for display controller.
 
 Naturally none of this is urgent and can be merged when suitable.
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Merge tag 'omap-for-v5.5/soc-late-signed' into omap-for-v5.5/ti-sysc-late

Few late SoC changes for v5.5 merge window

These changes just clean up few typos, and there is one non-critical
correction of missing put_device() after calling of_platform_populate()
for display controller.

Naturally none of this is urgent and can be merged when suitable.
This commit is contained in:
Tony Lindgren 2019-11-20 10:01:38 -08:00
parent b08a0c5775 0b491904f0
commit b82049f2c1
40 changed files with 468 additions and 434 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/am335x-icev2.dts
View File

@ -432,7 +432,7 @@ &mmc1 {
pinctrl-0 = <&mmc0_pins_default>;
};
&gpio0 {
&gpio0_target {
/* Do not idle the GPIO used for holding the VTT regulator */
ti,no-reset-on-init;
ti,no-idle-on-init;

6
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -127,7 +127,7 @@ target-module@5000 { /* 0x44e05000, ap 12 30.0 */
ranges = <0x0 0x5000 0x1000>;
};
target-module@7000 { /* 0x44e07000, ap 14 20.0 */
gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x7000 0x4>,
<0x7010 0x4>,
@ -2026,7 +2026,9 @@ target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
reg = <0xe000 0x4>,
<0xe054 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle ;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;

9
arch/arm/boot/dts/am3874-iceboard.dts
View File

@ -111,13 +111,13 @@ pca9548@70 {
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c-mux-idle-disconnect;
i2c@0 {
/* FMC A */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
i2c-mux-idle-disconnect;
};
i2c@1 {
@ -125,7 +125,6 @@ i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
i2c-mux-idle-disconnect;
};
i2c@2 {
@ -133,7 +132,6 @@ i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
i2c-mux-idle-disconnect;
};
i2c@3 {
@ -141,7 +139,6 @@ i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
i2c-mux-idle-disconnect;
};
i2c@4 {
@ -149,14 +146,12 @@ i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
i2c-mux-idle-disconnect;
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
i2c-mux-idle-disconnect;
ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
@ -182,14 +177,12 @@ i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
i2c-mux-idle-disconnect;
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
i2c-mux-idle-disconnect;
u41: pca9575@20 {
compatible = "nxp,pca9575";

2
arch/arm/boot/dts/am4372.dtsi
View File

@ -336,6 +336,8 @@ dispc: dispc@4832a400 {
ti,hwmods = "dss_dispc";
clocks = <&disp_clk>;
clock-names = "fck";
max-memory-bandwidth = <230000000>;
};
rfbi: rfbi@4832a800 {

48
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -2729,7 +2729,7 @@ mcasp1: mcasp@0 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx";
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>,
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
@ -2765,8 +2765,8 @@ mcasp2: mcasp@0 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
@ -2783,9 +2783,8 @@ target-module@68000 { /* 0x48468000, ap 13 26.0 */
<SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x68000 0x2000>,
@ -2801,7 +2800,7 @@ mcasp3: mcasp@0 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>,
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
@ -2818,9 +2817,8 @@ target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
<SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x6c000 0x2000>,
@ -2836,7 +2834,7 @@ mcasp4: mcasp@0 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>,
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
@ -2853,9 +2851,8 @@ target-module@70000 { /* 0x48470000, ap 19 36.0 */
<SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x70000 0x2000>,
@ -2871,7 +2868,7 @@ mcasp5: mcasp@0 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>,
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
@ -2888,9 +2885,8 @@ target-module@74000 { /* 0x48474000, ap 35 14.0 */
<SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x74000 0x2000>,
@ -2906,7 +2902,7 @@ mcasp6: mcasp@0 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>,
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
@ -2923,9 +2919,8 @@ target-module@78000 { /* 0x48478000, ap 39 0c.0 */
<SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x78000 0x2000>,
@ -2941,7 +2936,7 @@ mcasp7: mcasp@0 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>,
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
@ -2958,9 +2953,8 @@ target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
<SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x7c000 0x2000>,
@ -2976,7 +2970,7 @@ mcasp8: mcasp@0 {
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>,
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";

4
arch/arm/boot/dts/logicpd-torpedo-som.dtsi
View File

@ -192,3 +192,7 @@ twl_power: power {
&twl_gpio {
ti,use-leds;
};
&twl_keypad {
status = "disabled";
};

1
arch/arm/boot/dts/omap3-gta04.dtsi
View File

@ -124,6 +124,7 @@ lcd: td028ttec1@0 {
spi-max-frequency = <100000>;
spi-cpol;
spi-cpha;
spi-cs-high;
backlight= <&backlight>;
label = "lcd";

2
arch/arm/boot/dts/omap4-droid4-xt894.dts
View File

@ -369,7 +369,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1285", "ti,wl1283";
reg = <2>;
/* gpio_100 with gpmc_wait2 pad as wakeirq */
interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>,
interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x4e>;
interrupt-names = "irq", "wakeup";
ref-clock-frequency = <26000000>;

2
arch/arm/boot/dts/omap4-panda-common.dtsi
View File

@ -474,7 +474,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
/* gpio_53 with gpmc_ncs3 pad as wakeup */
interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>,
interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x3a>;
interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>;

2
arch/arm/boot/dts/omap4-sdp.dts
View File

@ -512,7 +512,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1281";
reg = <2>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>;
};

2
arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
View File

@ -69,7 +69,7 @@ wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
ref-clock-frequency = <38400000>;
};
};

2
arch/arm/boot/dts/omap5-board-common.dtsi
View File

@ -362,7 +362,7 @@ wlcore: wlcore@2 {
pinctrl-names = "default";
pinctrl-0 = <&wlcore_irq_pin>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_RISING>; /* gpio 14 */
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
ref-clock-frequency = <26000000>;
};
};

2
arch/arm/boot/dts/omap54xx-clocks.dtsi
View File

@ -1146,7 +1146,7 @@ dss_clkctrl: clk@20 {
};
};
gpu_cm: clock-controller@1500 {
gpu_cm: gpu_cm@1500 {
compatible = "ti,omap4-cm";
reg = <0x1500 0x100>;
#address-cells = <1>;

15
arch/arm/configs/omap2plus_defconfig
View File

@ -356,14 +356,15 @@ CONFIG_DRM_OMAP_CONNECTOR_HDMI=m
CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m
CONFIG_DRM_OMAP_PANEL_DPI=m
CONFIG_DRM_OMAP_PANEL_DSI_CM=m
CONFIG_DRM_OMAP_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_OMAP_PANEL_LGPHILIPS_LB035Q02=m
CONFIG_DRM_OMAP_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_OMAP_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_TILCDC=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_TI_TFP410=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
@ -423,6 +424,7 @@ CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_TEST=m
CONFIG_NOP_USB_XCEIV=m
CONFIG_AM335X_PHY_USB=m
@ -460,6 +462,7 @@ CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_CPCAP=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_GPIO=m
CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_PWM=m

33
arch/arm/mach-omap1/Kconfig
View File

@ -4,30 +4,25 @@ if ARCH_OMAP1
menu "TI OMAP1 specific features"
comment "OMAP Core Type"
depends on ARCH_OMAP1
config ARCH_OMAP730
depends on ARCH_OMAP1
bool "OMAP730 Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
select OMAP_MPU_TIMER
config ARCH_OMAP850
depends on ARCH_OMAP1
bool "OMAP850 Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
config ARCH_OMAP15XX
depends on ARCH_OMAP1
default y
bool "OMAP15xx Based System"
select CPU_ARM925T
select OMAP_MPU_TIMER
config ARCH_OMAP16XX
depends on ARCH_OMAP1
bool "OMAP16xx Based System"
select ARCH_OMAP_OTG
select CPU_ARM926T
@ -35,7 +30,6 @@ config ARCH_OMAP16XX
config OMAP_MUX
bool "OMAP multiplexing support"
depends on ARCH_OMAP
default y
help
Pin multiplexing support for OMAP boards. If your bootloader
@ -60,25 +54,24 @@ config OMAP_MUX_WARNINGS
printed, it's safe to deselect OMAP_MUX for your product.
comment "OMAP Board Type"
depends on ARCH_OMAP1
config MACH_OMAP_INNOVATOR
bool "TI Innovator"
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
depends on ARCH_OMAP15XX || ARCH_OMAP16XX
help
TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
have such a board.
config MACH_OMAP_H2
bool "TI H2 Support"
depends on ARCH_OMAP1 && ARCH_OMAP16XX
depends on ARCH_OMAP16XX
help
TI OMAP 1610/1611B H2 board support. Say Y here if you have such
a board.
config MACH_OMAP_H3
bool "TI H3 Support"
depends on ARCH_OMAP1 && ARCH_OMAP16XX
depends on ARCH_OMAP16XX
help
TI OMAP 1710 H3 board support. Say Y here if you have such
a board.
@ -91,7 +84,7 @@ config MACH_HERALD
config MACH_OMAP_OSK
bool "TI OSK Support"
depends on ARCH_OMAP1 && ARCH_OMAP16XX
depends on ARCH_OMAP16XX
help
TI OMAP 5912 OSK (OMAP Starter Kit) board support. Say Y here
if you have such a board.
@ -106,21 +99,21 @@ config OMAP_OSK_MISTRAL
config MACH_OMAP_PERSEUS2
bool "TI Perseus2"
depends on ARCH_OMAP1 && ARCH_OMAP730
depends on ARCH_OMAP730
help
Support for TI OMAP 730 Perseus2 board. Say Y here if you have such
a board.
config MACH_OMAP_FSAMPLE
bool "TI F-Sample"
depends on ARCH_OMAP1 && ARCH_OMAP730
depends on ARCH_OMAP730
help
Support for TI OMAP 850 F-Sample board. Say Y here if you have such
a board.
config MACH_OMAP_PALMTE
bool "Palm Tungsten E"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
depends on ARCH_OMAP15XX
help
Support for the Palm Tungsten E PDA. To boot the kernel, you'll
need a PalmOS compatible bootloader; check out
@ -129,7 +122,7 @@ config MACH_OMAP_PALMTE
config MACH_OMAP_PALMZ71
bool "Palm Zire71"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
depends on ARCH_OMAP15XX
help
Support for the Palm Zire71 PDA. To boot the kernel,
you'll need a PalmOS compatible bootloader; check out
@ -138,7 +131,7 @@ config MACH_OMAP_PALMZ71
config MACH_OMAP_PALMTT
bool "Palm Tungsten|T"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
depends on ARCH_OMAP15XX
help
Support for the Palm Tungsten|T PDA. To boot the kernel, you'll
need a PalmOS compatible bootloader (Garux); check out
@ -147,7 +140,7 @@ config MACH_OMAP_PALMTT
config MACH_SX1
bool "Siemens SX1"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
depends on ARCH_OMAP15XX
select I2C
help
Support for the Siemens SX1 phone. To boot the kernel,
@ -159,14 +152,14 @@ config MACH_SX1
config MACH_NOKIA770
bool "Nokia 770"
depends on ARCH_OMAP1 && ARCH_OMAP16XX
depends on ARCH_OMAP16XX
help
Support for the Nokia 770 Internet Tablet. Say Y here if you
have such a device.
config MACH_AMS_DELTA
bool "Amstrad E3 (Delta)"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
depends on ARCH_OMAP15XX
select FIQ
select GPIO_GENERIC_PLATFORM
select LEDS_GPIO_REGISTER
@ -178,7 +171,7 @@ config MACH_AMS_DELTA
config MACH_OMAP_GENERIC
bool "Generic OMAP board"
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
depends on ARCH_OMAP15XX || ARCH_OMAP16XX
help
Support for generic OMAP-1510, 1610 or 1710 board with
no FPGA. Can be used as template for porting Linux to

2
arch/arm/mach-omap1/ams-delta-fiq.c
View File

@ -110,7 +110,7 @@ void __init ams_delta_init_fiq(struct gpio_chip *chip,
/*
* FIQ handler takes full control over serio data and clk GPIO
* pins. Initiaize them and keep requested so nobody can
* pins. Initialize them and keep requested so nobody can
* interfere. Fail if any of those two couldn't be requested.
*/
switch (i) {

5
arch/arm/mach-omap2/Makefile
View File

@ -29,6 +29,11 @@ obj-y += mcbsp.o
endif
obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
ifneq ($(CONFIG_MFD_CPCAP),)
obj-y += pmic-cpcap.o
endif
obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
# SMP support ONLY available for OMAP4

78
arch/arm/mach-omap2/clockdomain.c
View File

@ -1147,7 +1147,21 @@ void clkdm_del_autodeps(struct clockdomain *clkdm)
/* Clockdomain-to-clock/hwmod framework interface code */
static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
/**
* clkdm_clk_enable - add an enabled downstream clock to this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the enabled downstream clock
*
* Increment the usecount of the clockdomain @clkdm and ensure that it
* is awake before @clk is enabled. Intended to be called by
* clk_enable() code. If the clockdomain is in software-supervised
* idle mode, force the clockdomain to wake. If the clockdomain is in
* hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
* ensure that devices in the clockdomain can be read from/written to
* by on-chip processors. Returns -EINVAL if passed null pointers;
* returns 0 upon success or if the clockdomain is in hwsup idle mode.
*/
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *unused)
{
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
return -EINVAL;
@ -1174,33 +1188,6 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
return 0;
}
/**
* clkdm_clk_enable - add an enabled downstream clock to this clkdm
* @clkdm: struct clockdomain *
* @clk: struct clk * of the enabled downstream clock
*
* Increment the usecount of the clockdomain @clkdm and ensure that it
* is awake before @clk is enabled. Intended to be called by
* clk_enable() code. If the clockdomain is in software-supervised
* idle mode, force the clockdomain to wake. If the clockdomain is in
* hardware-supervised idle mode, add clkdm-pwrdm autodependencies, to
* ensure that devices in the clockdomain can be read from/written to
* by on-chip processors. Returns -EINVAL if passed null pointers;
* returns 0 upon success or if the clockdomain is in hwsup idle mode.
*/
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
{
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream clocks for debugging purposes?
*/
if (!clk)
return -EINVAL;
return _clkdm_clk_hwmod_enable(clkdm);
}
/**
* clkdm_clk_disable - remove an enabled downstream clock from this clkdm
* @clkdm: struct clockdomain *
@ -1216,13 +1203,13 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
*/
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
return -EINVAL;
pwrdm_lock(clkdm->pwrdm.ptr);
/* corner case: disabling unused clocks */
if ((__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
if (clk && (__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
goto ccd_exit;
if (clkdm->usecount == 0) {
@ -1277,7 +1264,7 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
if (!oh)
return -EINVAL;
return _clkdm_clk_hwmod_enable(clkdm);
return clkdm_clk_enable(clkdm, NULL);
}
/**
@ -1300,35 +1287,10 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
/*
* XXX Rewrite this code to maintain a list of enabled
* downstream hwmods for debugging purposes?
*/
if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
if (!oh)
return -EINVAL;
pwrdm_lock(clkdm->pwrdm.ptr);
if (clkdm->usecount == 0) {
pwrdm_unlock(clkdm->pwrdm.ptr);
WARN_ON(1); /* underflow */
return -ERANGE;
}
clkdm->usecount--;
if (clkdm->usecount > 0) {
pwrdm_unlock(clkdm->pwrdm.ptr);
return 0;
}
arch_clkdm->clkdm_clk_disable(clkdm);
pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
pwrdm_unlock(clkdm->pwrdm.ptr);
pr_debug("clockdomain: %s: disabled\n", clkdm->name);
return 0;
return clkdm_clk_disable(clkdm, NULL);
}
/**

4
arch/arm/mach-omap2/control.c
View File

@ -684,7 +684,7 @@ static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)];
*
* Save the wkup domain registers
*/
void am43xx_control_save_context(void)
static void am43xx_control_save_context(void)
{
int i;
@ -698,7 +698,7 @@ void am43xx_control_save_context(void)
*
* Restore the wkup domain registers
*/
void am43xx_control_restore_context(void)
static void am43xx_control_restore_context(void)
{
int i;

1
arch/arm/mach-omap2/control.h
View File

@ -195,6 +195,7 @@
#define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243
#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246
#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB 0x24C
#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A

1
arch/arm/mach-omap2/display.c
View File

@ -265,6 +265,7 @@ static int __init omapdss_init_of(void)
r = of_platform_populate(node, NULL, NULL, &pdev->dev);
if (r) {
pr_err("Unable to populate DSS submodule devices\n");
put_device(&pdev->dev);
return r;
}

2
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View File

@ -227,7 +227,6 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
unsigned int wakeup_cpu;
if (omap_rev() == OMAP4430_REV_ES1_0)
return -ENXIO;
@ -292,7 +291,6 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
* secure devices, CPUx does WFI which can result in
* domain transition
*/
wakeup_cpu = smp_processor_id();
pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
pwrdm_post_transition(NULL);

19
arch/arm/mach-omap2/omap_device.c
View File

@ -119,11 +119,7 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
/**
* omap_device_build_from_dt - build an omap_device with multiple hwmods
* @pdev_name: name of the platform_device driver to use
* @pdev_id: this platform_device's connection ID
* @oh: ptr to the single omap_hwmod that backs this omap_device
* @pdata: platform_data ptr to associate with the platform_device
* @pdata_len: amount of memory pointed to by @pdata
* @pdev: The platform device to update.
*
* Function for building an omap_device already registered from device-tree
*
@ -292,7 +288,7 @@ static int _omap_device_idle_hwmods(struct omap_device *od)
/**
* omap_device_get_context_loss_count - get lost context count
* @od: struct omap_device *
* @pdev: The platform device to update.
*
* Using the primary hwmod, query the context loss count for this
* device.
@ -321,9 +317,8 @@ int omap_device_get_context_loss_count(struct platform_device *pdev)
/**
* omap_device_alloc - allocate an omap_device
* @pdev: platform_device that will be included in this omap_device
* @oh: ptr to the single omap_hwmod that backs this omap_device
* @pdata: platform_data ptr to associate with the platform_device
* @pdata_len: amount of memory pointed to by @pdata
* @ohs: ptr to the omap_hwmod for this omap_device
* @oh_cnt: the size of the ohs list
*
* Convenience function for allocating an omap_device structure and filling
* hwmods, and resources.
@ -649,7 +644,7 @@ struct dev_pm_domain omap_device_pm_domain = {
/**
* omap_device_register - register an omap_device with one omap_hwmod
* @od: struct omap_device * to register
* @pdev: the platform device (omap_device) to register.
*
* Register the omap_device structure. This currently just calls
* platform_device_register() on the underlying platform_device.
@ -668,7 +663,7 @@ int omap_device_register(struct platform_device *pdev)
/**
* omap_device_enable - fully activate an omap_device
* @od: struct omap_device * to activate
* @pdev: the platform device to activate
*
* Do whatever is necessary for the hwmods underlying omap_device @od
* to be accessible and ready to operate. This generally involves
@ -702,7 +697,7 @@ int omap_device_enable(struct platform_device *pdev)
/**
* omap_device_idle - idle an omap_device
* @od: struct omap_device * to idle
* @pdev: The platform_device (omap_device) to idle
*
* Idle omap_device @od. Device drivers call this function indirectly
* via pm_runtime_put*(). Returns -EINVAL if the omap_device is not

97
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -623,39 +623,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
return 0;
}
/**
* _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
* @oh: struct omap_hwmod *
*
* Prevent the hardware module @oh to send wakeups. Returns -EINVAL
* upon error or 0 upon success.
*/
static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
{
if (!oh->class->sysc ||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
(oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
(oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
return -EINVAL;
if (!oh->class->sysc->sysc_fields) {
WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
return -EINVAL;
}
if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
*v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
_set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
return 0;
}
static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
{
struct clk_hw_omap *clk;
@ -3867,70 +3834,6 @@ void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
* for context save/restore operations?
*/
/**
* omap_hwmod_enable_wakeup - allow device to wake up the system
* @oh: struct omap_hwmod *
*
* Sets the module OCP socket ENAWAKEUP bit to allow the module to
* send wakeups to the PRCM, and enable I/O ring wakeup events for
* this IP block if it has dynamic mux entries. Eventually this
* should set PRCM wakeup registers to cause the PRCM to receive
* wakeup events from the module. Does not set any wakeup routing
* registers beyond this point - if the module is to wake up any other
* module or subsystem, that must be set separately. Called by
* omap_device code. Returns -EINVAL on error or 0 upon success.
*/
int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
{
unsigned long flags;
u32 v;
spin_lock_irqsave(&oh->_lock, flags);
if (oh->class->sysc &&
(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
v = oh->_sysc_cache;
_enable_wakeup(oh, &v);
_write_sysconfig(v, oh);
}
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;
}
/**
* omap_hwmod_disable_wakeup - prevent device from waking the system
* @oh: struct omap_hwmod *
*
* Clears the module OCP socket ENAWAKEUP bit to prevent the module
* from sending wakeups to the PRCM, and disable I/O ring wakeup
* events for this IP block if it has dynamic mux entries. Eventually
* this should clear PRCM wakeup registers to cause the PRCM to ignore
* wakeup events from the module. Does not set any wakeup routing
* registers beyond this point - if the module is to wake up any other
* module or subsystem, that must be set separately. Called by
* omap_device code. Returns -EINVAL on error or 0 upon success.
*/
int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
{
unsigned long flags;
u32 v;
spin_lock_irqsave(&oh->_lock, flags);
if (oh->class->sysc &&
(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
v = oh->_sysc_cache;
_disable_wakeup(oh, &v);
_write_sysconfig(v, oh);
}
spin_unlock_irqrestore(&oh->_lock, flags);
return 0;
}
/**
* omap_hwmod_assert_hardreset - assert the HW reset line of submodules
* contained in the hwmod module.

3
arch/arm/mach-omap2/omap_hwmod.h
View File

@ -646,9 +646,6 @@ int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
int omap_hwmod_for_each_by_class(const char *classname,
int (*fn)(struct omap_hwmod *oh,
void *user),

3
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View File

@ -583,7 +583,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_RESET_STATUS,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,

5
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View File

@ -230,8 +230,9 @@ static struct omap_hwmod am33xx_control_hwmod = {
static struct omap_hwmod_class_sysconfig lcdc_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x54,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
.sysc_fields = &omap_hwmod_sysc_type2,
};

4
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@ -790,7 +790,7 @@ static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
.sysc = &omap44xx_sha0_sysc,
};
struct omap_hwmod omap44xx_sha0_hwmod = {
static struct omap_hwmod omap44xx_sha0_hwmod = {
.name = "sham",
.class = &omap44xx_sha0_hwmod_class,
.clkdm_name = "l4_secure_clkdm",
@ -974,7 +974,7 @@ static struct omap_hwmod omap44xx_des_hwmod = {
},
};
struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_des_hwmod,
.clk = "l3_div_ck",

2
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -682,7 +682,7 @@ static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
.sysc = &dra7xx_sha0_sysc,
};
struct omap_hwmod dra7xx_sha0_hwmod = {
static struct omap_hwmod dra7xx_sha0_hwmod = {
.name = "sham",
.class = &dra7xx_sha0_hwmod_class,
.clkdm_name = "l4sec_clkdm",

8
arch/arm/mach-omap2/omap_twl.c
View File

@ -36,11 +36,6 @@
#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
static bool is_offset_valid;
static u8 smps_offset;
@ -219,7 +214,8 @@ int __init omap4_twl_init(void)
{
struct voltagedomain *voltdm;
if (!cpu_is_omap44xx())
if (!cpu_is_omap44xx() ||
of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
return -ENODEV;
voltdm = voltdm_lookup("mpu");

16
arch/arm/mach-omap2/opp4xxx_data.c
View File

@ -32,20 +32,22 @@
#define OMAP4430_VDD_MPU_OPP50_UV 1025000
#define OMAP4430_VDD_MPU_OPP100_UV 1200000
#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
#define OMAP4430_VDD_MPU_OPPTURBO_UV 1325000
#define OMAP4430_VDD_MPU_OPPNITRO_UV 1388000
#define OMAP4430_VDD_MPU_OPPNITROSB_UV 1398000
struct omap_volt_data omap443x_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITROSB_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB, 0xfa, 0x27),
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
#define OMAP4430_VDD_IVA_OPP50_UV 1013000
#define OMAP4430_VDD_IVA_OPP100_UV 1188000
#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000
#define OMAP4430_VDD_IVA_OPP50_UV 950000
#define OMAP4430_VDD_IVA_OPP100_UV 1114000
#define OMAP4430_VDD_IVA_OPPTURBO_UV 1291000
struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
@ -54,8 +56,8 @@ struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(0, 0, 0, 0),
};
#define OMAP4430_VDD_CORE_OPP50_UV 1025000
#define OMAP4430_VDD_CORE_OPP100_UV 1200000
#define OMAP4430_VDD_CORE_OPP50_UV 962000
#define OMAP4430_VDD_CORE_OPP100_UV 1127000
struct omap_volt_data omap443x_vdd_core_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),

52
arch/arm/mach-omap2/pdata-quirks.c
View File

@ -11,7 +11,6 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/ti_wilink_st.h>
#include <linux/wl12xx.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
@ -139,53 +138,6 @@ static void __init omap3_sbc_t3530_legacy_init(void)
omap3_sbc_t3x_usb_hub_init(167, "sb-t35 usb hub");
}
static struct ti_st_plat_data wilink_pdata = {
.nshutdown_gpio = 137,
.dev_name = "/dev/ttyO1",
.flow_cntrl = 1,
.baud_rate = 300000,
};
static struct platform_device wl18xx_device = {
.name = "kim",
.id = -1,
.dev = {
.platform_data = &wilink_pdata,
}
};
static struct ti_st_plat_data wilink7_pdata = {
.nshutdown_gpio = 162,
.dev_name = "/dev/ttyO1",
.flow_cntrl = 1,
.baud_rate = 3000000,
};
static struct platform_device wl128x_device = {
.name = "kim",
.id = -1,
.dev = {
.platform_data = &wilink7_pdata,
}
};
static struct platform_device btwilink_device = {
.name = "btwilink",
.id = -1,
};
static void __init omap3_igep0020_rev_f_legacy_init(void)
{
platform_device_register(&wl18xx_device);
platform_device_register(&btwilink_device);
}
static void __init omap3_igep0030_rev_g_legacy_init(void)
{
platform_device_register(&wl18xx_device);
platform_device_register(&btwilink_device);
}
static void __init omap3_evm_legacy_init(void)
{
hsmmc2_internal_input_clk();
@ -299,8 +251,6 @@ static void __init omap3_tao3530_legacy_init(void)
static void __init omap3_logicpd_torpedo_init(void)
{
omap3_gpio126_127_129();
platform_device_register(&wl128x_device);
platform_device_register(&btwilink_device);
}
/* omap3pandora legacy devices */
@ -679,8 +629,6 @@ static struct pdata_init pdata_quirks[] __initdata = {
{ "nokia,omap3-n900", nokia_n900_legacy_init, },
{ "nokia,omap3-n9", hsmmc2_internal_input_clk, },
{ "nokia,omap3-n950", hsmmc2_internal_input_clk, },
{ "isee,omap3-igep0020-rev-f", omap3_igep0020_rev_f_legacy_init, },
{ "isee,omap3-igep0030-rev-g", omap3_igep0030_rev_g_legacy_init, },
{ "logicpd,dm3730-torpedo-devkit", omap3_logicpd_torpedo_init, },
{ "ti,omap3-evm-37xx", omap3_evm_legacy_init, },
{ "ti,am3517-evm", am3517_evm_legacy_init, },

101
arch/arm/mach-omap2/pm.c
View File

@ -74,83 +74,6 @@ int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
return 0;
}
/*
* This API is to be called during init to set the various voltage
* domains to the voltage as per the opp table. Typically we boot up
* at the nominal voltage. So this function finds out the rate of
* the clock associated with the voltage domain, finds out the correct
* opp entry and sets the voltage domain to the voltage specified
* in the opp entry
*/
static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
const char *oh_name)
{
struct voltagedomain *voltdm;
struct clk *clk;
struct dev_pm_opp *opp;
unsigned long freq, bootup_volt;
struct device *dev;
if (!vdd_name || !clk_name || !oh_name) {
pr_err("%s: invalid parameters\n", __func__);
goto exit;
}
if (!strncmp(oh_name, "mpu", 3))
/*
* All current OMAPs share voltage rail and clock
* source, so CPU0 is used to represent the MPU-SS.
*/
dev = get_cpu_device(0);
else
dev = omap_device_get_by_hwmod_name(oh_name);
if (IS_ERR(dev)) {
pr_err("%s: Unable to get dev pointer for hwmod %s\n",
__func__, oh_name);
goto exit;
}
voltdm = voltdm_lookup(vdd_name);
if (!voltdm) {
pr_err("%s: unable to get vdd pointer for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
clk = clk_get(NULL, clk_name);
if (IS_ERR(clk)) {
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
goto exit;
}
freq = clk_get_rate(clk);
clk_put(clk);
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
if (IS_ERR(opp)) {
pr_err("%s: unable to find boot up OPP for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
bootup_volt = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
if (!bootup_volt) {
pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
voltdm_scale(voltdm, bootup_volt);
return 0;
exit:
pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
return -EINVAL;
}
#ifdef CONFIG_SUSPEND
static int omap_pm_enter(suspend_state_t suspend_state)
{
@ -208,25 +131,6 @@ void omap_common_suspend_init(void *pm_suspend)
}
#endif /* CONFIG_SUSPEND */
static void __init omap3_init_voltages(void)
{
if (!soc_is_omap34xx())
return;
omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
omap2_set_init_voltage("core", "l3_ick", "l3_main");
}
static void __init omap4_init_voltages(void)
{
if (!soc_is_omap44xx())
return;
omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
}
int __maybe_unused omap_pm_nop_init(void)
{
return 0;
@ -244,12 +148,9 @@ int __init omap2_common_pm_late_init(void)
/* Init the voltage layer */
omap3_twl_init();
omap4_twl_init();
omap4_cpcap_init();
omap_voltage_late_init();
/* Initialize the voltages */
omap3_init_voltages();
omap4_init_voltages();
/* Smartreflex device init */
omap_devinit_smartreflex();

14
arch/arm/mach-omap2/pm.h
View File

@ -107,6 +107,11 @@ extern u16 pm44xx_errata;
#define IS_PM44XX_ERRATUM(id) 0
#endif
#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
#ifdef CONFIG_POWER_AVS_OMAP
extern int omap_devinit_smartreflex(void);
extern void omap_enable_smartreflex_on_init(void);
@ -134,6 +139,15 @@ static inline int omap4_twl_init(void)
}
#endif
#if IS_ENABLED(CONFIG_MFD_CPCAP)
extern int omap4_cpcap_init(void);
#else
static inline int omap4_cpcap_init(void)
{
return -EINVAL;
}
#endif
#ifdef CONFIG_PM
extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);

13
arch/arm/mach-omap2/pm44xx.c
View File

@ -128,18 +128,9 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
return 0;
}
/*
* Bootloader or kexec boot may have LOGICRETSTATE cleared
* for some domains. This is the case when kexec booting from
* Android kernels that support off mode for example.
* Make sure it's set at least for core and per, otherwise
* we currently will see lost GPIO interrupts for wlcore and
* smsc911x at least if per hits retention during idle.
*/
if (!strncmp(pwrdm->name, "core", 4) ||
!strncmp(pwrdm->name, "l4per", 5) ||
!strncmp(pwrdm->name, "wkup", 4))
pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET);
!strncmp(pwrdm->name, "l4per", 5))
pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF);
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
if (!pwrst)

271
arch/arm/mach-omap2/pmic-cpcap.c Normal file
View File

@ -0,0 +1,271 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* pmic-cpcap.c - CPCAP-specific functions for the OPP code
*
* Adapted from Motorola Mapphone Android Linux kernel
* Copyright (C) 2011 Motorola, Inc.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "soc.h"
#include "pm.h"
#include "voltage.h"
#include <linux/init.h>
#include "vc.h"
/**
* omap_cpcap_vsel_to_vdc - convert CPCAP VSEL value to microvolts DC
* @vsel: CPCAP VSEL value to convert
*
* Returns the microvolts DC that the CPCAP PMIC should generate when
* programmed with @vsel.
*/
static unsigned long omap_cpcap_vsel_to_uv(unsigned char vsel)
{
if (vsel > 0x44)
vsel = 0x44;
return (((vsel * 125) + 6000)) * 100;
}
/**
* omap_cpcap_uv_to_vsel - convert microvolts DC to CPCAP VSEL value
* @uv: microvolts DC to convert
*
* Returns the VSEL value necessary for the CPCAP PMIC to
* generate an output voltage equal to or greater than @uv microvolts DC.
*/
static unsigned char omap_cpcap_uv_to_vsel(unsigned long uv)
{
if (uv < 600000)
uv = 600000;
else if (uv > 1450000)
uv = 1450000;
return DIV_ROUND_UP(uv - 600000, 12500);
}
static struct omap_voltdm_pmic omap_cpcap_core = {
.slew_rate = 4000,
.step_size = 12500,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 900000,
.vddmax = 1350000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x02,
.volt_reg_addr = 0x00,
.cmd_reg_addr = 0x01,
.i2c_high_speed = false,
.vsel_to_uv = omap_cpcap_vsel_to_uv,
.uv_to_vsel = omap_cpcap_uv_to_vsel,
};
static struct omap_voltdm_pmic omap_cpcap_iva = {
.slew_rate = 4000,
.step_size = 12500,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 900000,
.vddmax = 1350000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x44,
.volt_reg_addr = 0x0,
.cmd_reg_addr = 0x01,
.i2c_high_speed = false,
.vsel_to_uv = omap_cpcap_vsel_to_uv,
.uv_to_vsel = omap_cpcap_uv_to_vsel,
};
/**
* omap_max8952_vsel_to_vdc - convert MAX8952 VSEL value to microvolts DC
* @vsel: MAX8952 VSEL value to convert
*
* Returns the microvolts DC that the MAX8952 Regulator should generate when
* programmed with @vsel.
*/
static unsigned long omap_max8952_vsel_to_uv(unsigned char vsel)
{
if (vsel > 0x3F)
vsel = 0x3F;
return (((vsel * 100) + 7700)) * 100;
}
/**
* omap_max8952_uv_to_vsel - convert microvolts DC to MAX8952 VSEL value
* @uv: microvolts DC to convert
*
* Returns the VSEL value necessary for the MAX8952 Regulator to
* generate an output voltage equal to or greater than @uv microvolts DC.
*/
static unsigned char omap_max8952_uv_to_vsel(unsigned long uv)
{
if (uv < 770000)
uv = 770000;
else if (uv > 1400000)
uv = 1400000;
return DIV_ROUND_UP(uv - 770000, 10000);
}
static struct omap_voltdm_pmic omap443x_max8952_mpu = {
.slew_rate = 16000,
.step_size = 10000,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 900000,
.vddmax = 1400000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x60,
.volt_reg_addr = 0x03,
.cmd_reg_addr = 0x03,
.i2c_high_speed = false,
.vsel_to_uv = omap_max8952_vsel_to_uv,
.uv_to_vsel = omap_max8952_uv_to_vsel,
};
/**
* omap_fan5355_vsel_to_vdc - convert FAN535503 VSEL value to microvolts DC
* @vsel: FAN535503 VSEL value to convert
*
* Returns the microvolts DC that the FAN535503 Regulator should generate when
* programmed with @vsel.
*/
static unsigned long omap_fan535503_vsel_to_uv(unsigned char vsel)
{
/* Extract bits[5:0] */
vsel &= 0x3F;
return (((vsel * 125) + 7500)) * 100;
}
/**
* omap_fan535508_vsel_to_vdc - convert FAN535508 VSEL value to microvolts DC
* @vsel: FAN535508 VSEL value to convert
*
* Returns the microvolts DC that the FAN535508 Regulator should generate when
* programmed with @vsel.
*/
static unsigned long omap_fan535508_vsel_to_uv(unsigned char vsel)
{
/* Extract bits[5:0] */
vsel &= 0x3F;
if (vsel > 0x37)
vsel = 0x37;
return (((vsel * 125) + 7500)) * 100;
}
/**
* omap_fan535503_uv_to_vsel - convert microvolts DC to FAN535503 VSEL value
* @uv: microvolts DC to convert
*
* Returns the VSEL value necessary for the MAX8952 Regulator to
* generate an output voltage equal to or greater than @uv microvolts DC.
*/
static unsigned char omap_fan535503_uv_to_vsel(unsigned long uv)
{
unsigned char vsel;
if (uv < 750000)
uv = 750000;
else if (uv > 1537500)
uv = 1537500;
vsel = DIV_ROUND_UP(uv - 750000, 12500);
return vsel | 0xC0;
}
/**
* omap_fan535508_uv_to_vsel - convert microvolts DC to FAN535508 VSEL value
* @uv: microvolts DC to convert
*
* Returns the VSEL value necessary for the MAX8952 Regulator to
* generate an output voltage equal to or greater than @uv microvolts DC.
*/
static unsigned char omap_fan535508_uv_to_vsel(unsigned long uv)
{
unsigned char vsel;
if (uv < 750000)
uv = 750000;
else if (uv > 1437500)
uv = 1437500;
vsel = DIV_ROUND_UP(uv - 750000, 12500);
return vsel | 0xC0;
}
/* fan5335-core */
static struct omap_voltdm_pmic omap4_fan_core = {
.slew_rate = 4000,
.step_size = 12500,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 850000,
.vddmax = 1375000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x4A,
.i2c_high_speed = false,
.volt_reg_addr = 0x01,
.cmd_reg_addr = 0x01,
.vsel_to_uv = omap_fan535508_vsel_to_uv,
.uv_to_vsel = omap_fan535508_uv_to_vsel,
};
/* fan5335 iva */
static struct omap_voltdm_pmic omap4_fan_iva = {
.slew_rate = 4000,
.step_size = 12500,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 850000,
.vddmax = 1375000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x48,
.volt_reg_addr = 0x01,
.cmd_reg_addr = 0x01,
.i2c_high_speed = false,
.vsel_to_uv = omap_fan535503_vsel_to_uv,
.uv_to_vsel = omap_fan535503_uv_to_vsel,
};
int __init omap4_cpcap_init(void)
{
struct voltagedomain *voltdm;
if (!of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
return -ENODEV;
voltdm = voltdm_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap443x_max8952_mpu);
if (of_machine_is_compatible("motorola,droid-bionic")) {
voltdm = voltdm_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap_cpcap_core);
voltdm = voltdm_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap_cpcap_iva);
} else {
voltdm = voltdm_lookup("core");
omap_voltage_register_pmic(voltdm, &omap4_fan_core);
voltdm = voltdm_lookup("iva");
omap_voltage_register_pmic(voltdm, &omap4_fan_iva);
}
return 0;
}
static int __init cpcap_late_init(void)
{
omap4_vc_set_pmic_signaling(PWRDM_POWER_RET);
return 0;
}
omap_late_initcall(cpcap_late_init);

4
arch/arm/mach-omap2/prm44xx.c
View File

@ -745,7 +745,7 @@ struct pwrdm_ops omap4_pwrdm_operations = {
static int omap44xx_prm_late_init(void);
void prm_save_context(void)
static void prm_save_context(void)
{
omap_prm_context.irq_enable =
omap4_prm_read_inst_reg(AM43XX_PRM_OCP_SOCKET_INST,
@ -756,7 +756,7 @@ void prm_save_context(void)
omap4_prcm_irq_setup.pm_ctrl);
}
void prm_restore_context(void)
static void prm_restore_context(void)
{
omap4_prm_write_inst_reg(omap_prm_context.irq_enable,
OMAP4430_PRM_OCP_SOCKET_INST,

57
arch/arm/mach-omap2/vc.c
View File

@ -26,6 +26,31 @@
#include "scrm44xx.h"
#include "control.h"
#define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14)
#define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13)
#define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12)
#define OMAP4430_VDD_IVA_PRESENCE BIT(9)
#define OMAP4430_VDD_MPU_PRESENCE BIT(8)
#define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4)
#define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2)
#define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0)
#define OMAP4430_AUTO_CTRL_VDD_RET 2
#define OMAP4430_VDD_I2C_DISABLE_MASK \
(OMAP4430_VDD_IVA_I2C_DISABLE | \
OMAP4430_VDD_MPU_I2C_DISABLE | \
OMAP4430_VDD_CORE_I2C_DISABLE)
#define OMAP4_VDD_DEFAULT_VAL \
(OMAP4430_VDD_I2C_DISABLE_MASK | \
OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \
OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \
OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \
OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET))
#define OMAP4_VDD_RET_VAL \
(OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK)
/**
* struct omap_vc_channel_cfg - describe the cfg_channel bitfield
* @sa: bit for slave address
@ -280,6 +305,26 @@ void omap3_vc_set_pmic_signaling(int core_next_state)
}
}
void omap4_vc_set_pmic_signaling(int core_next_state)
{
struct voltagedomain *vd = vc.vd;
u32 val;
if (!vd)
return;
switch (core_next_state) {
case PWRDM_POWER_RET:
val = OMAP4_VDD_RET_VAL;
break;
default:
val = OMAP4_VDD_DEFAULT_VAL;
break;
}
vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET);
}
/*
* Configure signal polarity for sys_clkreq and sys_off_mode pins
* as the default values are wrong and can cause the system to hang
@ -542,9 +587,19 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
}
static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm)
{
if (vc.vd)
return;
vc.vd = voltdm;
voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET);
}
/* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{
omap4_vc_init_pmic_signaling(voltdm);
omap4_set_timings(voltdm, true);
omap4_set_timings(voltdm, false);
}
@ -615,7 +670,7 @@ static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
const struct i2c_init_data *i2c_data;
if (!voltdm->pmic->i2c_high_speed) {
pr_warn("%s: only high speed supported!\n", __func__);
pr_info("%s: using bootloader low-speed timings\n", __func__);
return;
}

2
arch/arm/mach-omap2/vc.h
View File

@ -117,7 +117,7 @@ extern struct omap_vc_param omap4_iva_vc_data;
extern struct omap_vc_param omap4_core_vc_data;
void omap3_vc_set_pmic_signaling(int core_next_state);
void omap4_vc_set_pmic_signaling(int core_next_state);
void omap_vc_init_channel(struct voltagedomain *voltdm);
int omap_vc_pre_scale(struct voltagedomain *voltdm,

6
drivers/clk/ti/clk-7xx.c
View File

@ -683,7 +683,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
@ -828,8 +828,8 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),