mirror of https://gitee.com/openkylin/linux.git
i40e/i40evf: add VIRTCHNL_VF_OFFLOAD flag
Add virtual channel offload capability to support RX polling mode in the VF. Change-ID: Ib643ae2a7506dfc75fc489fc207493fabefa4832 Signed-off-by: Jingjing Wu <jingjing.wu@intel.com> Signed-off-by: Anjali Singhai Jain <anjali.singhai@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -873,6 +873,13 @@
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#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
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#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31
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#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)
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#define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */
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#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT 0
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#define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT)
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#define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1
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#define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT)
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#define I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT 2
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#define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT)
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#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */
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#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0
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#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
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@ -152,6 +152,7 @@ struct i40e_virtchnl_vsi_resource {
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#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ 0x00000008
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#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG 0x00000010
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#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000
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#define I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING 0x00020000
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struct i40e_virtchnl_vf_resource {
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u16 num_vsis;
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@ -335,6 +335,18 @@ static void i40e_config_irq_link_list(struct i40e_vf *vf, u16 vsi_id,
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wr32(hw, reg_idx, reg);
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}
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/* if the vf is running in polling mode and using interrupt zero,
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* need to disable auto-mask on enabling zero interrupt for VFs.
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*/
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if ((vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING) &&
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(vector_id == 0)) {
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reg = rd32(hw, I40E_GLINT_CTL);
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if (!(reg & I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK)) {
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reg |= I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
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wr32(hw, I40E_GLINT_CTL, reg);
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}
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}
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irq_list_done:
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i40e_flush(hw);
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}
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@ -152,6 +152,7 @@ struct i40e_virtchnl_vsi_resource {
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#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ 0x00000008
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#define I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG 0x00000010
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#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000
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#define I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING 0x00020000
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struct i40e_virtchnl_vf_resource {
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u16 num_vsis;
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