mirror of https://gitee.com/openkylin/linux.git
dmaengine: xilinx_dma: Drop SG support for VDMA IP
xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -1102,6 +1102,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
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struct xilinx_dma_tx_descriptor *desc, *tail_desc;
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u32 reg, j;
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struct xilinx_vdma_tx_segment *tail_segment;
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struct xilinx_vdma_tx_segment *segment, *last = NULL;
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int i = 0;
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/* This function was invoked with lock held */
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if (chan->err)
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@ -1121,14 +1123,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
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tail_segment = list_last_entry(&tail_desc->segments,
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struct xilinx_vdma_tx_segment, node);
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/*
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* If hardware is idle, then all descriptors on the running lists are
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* done, start new transfers
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*/
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if (chan->has_sg)
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dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
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desc->async_tx.phys);
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/* Configure the hardware using info in the config structure */
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if (chan->has_vflip) {
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reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP);
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@ -1145,15 +1139,11 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
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else
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reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN;
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/*
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* With SG, start with circular mode, so that BDs can be fetched.
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* In direct register mode, if not parking, enable circular mode
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*/
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if (chan->has_sg || !config->park)
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reg |= XILINX_DMA_DMACR_CIRC_EN;
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/* If not parking, enable circular mode */
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if (config->park)
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reg &= ~XILINX_DMA_DMACR_CIRC_EN;
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else
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reg |= XILINX_DMA_DMACR_CIRC_EN;
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dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
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@ -1175,15 +1165,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
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return;
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/* Start the transfer */
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if (chan->has_sg) {
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dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
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tail_segment->phys);
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list_splice_tail_init(&chan->pending_list, &chan->active_list);
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chan->desc_pendingcount = 0;
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} else {
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struct xilinx_vdma_tx_segment *segment, *last = NULL;
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int i = 0;
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if (chan->desc_submitcount < chan->num_frms)
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i = chan->desc_submitcount;
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@ -1216,7 +1197,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan)
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list_add_tail(&desc->node, &chan->active_list);
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if (chan->desc_submitcount == chan->num_frms)
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chan->desc_submitcount = 0;
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}
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chan->idle = false;
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}
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