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Merge branch 'remotes/lorenzo/pci/dwc' 

- Make kirin_dw_pcie_ops constant (Nishka Dasgupta)

  - Make DesignWare "num-lanes" property optional and remove from relevant
    DTs (Hou Zhiqiang)

* remotes/lorenzo/pci/dwc:
  arm64: dts: fsl: Remove num-lanes property from PCIe nodes
  ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes
  PCI: dwc: Return directly when num-lanes is not found
  dt-bindings: PCI: designware: Remove the num-lanes from Required properties
  PCI: kirin: Make structure kirin_dw_pcie_ops constant
This commit is contained in:
Bjorn Helgaas 2019-09-23 16:10:18 -05:00
parent af47f25f33 4035ff36a6
commit b83e445d46
9 changed files with 5 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/pci/designware-pcie.txt
View File

@ -11,7 +11,6 @@ Required properties:
the ATU address space.
(The old way of getting the configuration address space from "ranges"
is deprecated and should be avoided.)
- num-lanes: number of lanes to use
RC mode:
- #address-cells: set to <3>
- #size-cells: set to <2>

2
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -874,7 +874,6 @@ pcie@3400000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -899,7 +898,6 @@ pcie@3500000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */

1
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -486,7 +486,6 @@ pcie: pcie@3400000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <4>;
num-viewport = <2>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */

3
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -677,7 +677,6 @@ pcie@3400000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -704,7 +703,6 @@ pcie@3500000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <2>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -731,7 +729,6 @@ pcie@3600000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <2>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */

6
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -649,7 +649,6 @@ pcie@3400000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -671,7 +670,6 @@ pcie_ep@3400000 {
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
num-lanes = <2>;
status = "disabled";
};
@ -687,7 +685,6 @@ pcie@3500000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <2>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -709,7 +706,6 @@ pcie_ep@3500000 {
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
num-lanes = <2>;
status = "disabled";
};
@ -725,7 +721,6 @@ pcie@3600000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <2>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -747,7 +742,6 @@ pcie_ep@3600000 {
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
num-lanes = <2>;
status = "disabled";
};

3
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -452,7 +452,6 @@ pcie@3400000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <256>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -478,7 +477,6 @@ pcie@3500000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -504,7 +502,6 @@ pcie@3600000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <8>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */

4
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -634,7 +634,6 @@ pcie1: pcie@3400000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
@ -656,7 +655,6 @@ pcie2: pcie@3500000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
@ -678,7 +676,6 @@ pcie3: pcie@3600000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <8>;
num-viewport = <256>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
@ -700,7 +697,6 @@ pcie4: pcie@3700000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;

6
drivers/pci/controller/dwc/pcie-designware.c
View File

@ -423,8 +423,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
ret = of_property_read_u32(np, "num-lanes", &lanes);
if (ret)
lanes = 0;
if (ret) {
dev_dbg(pci->dev, "property num-lanes isn't found\n");
return;
}
/* Set the number of lanes */
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);

2
drivers/pci/controller/dwc/pcie-kirin.c
View File

@ -436,7 +436,7 @@ static int kirin_pcie_host_init(struct pcie_port *pp)
return 0;
}
static struct dw_pcie_ops kirin_dw_pcie_ops = {
static const struct dw_pcie_ops kirin_dw_pcie_ops = {
.read_dbi = kirin_pcie_read_dbi,
.write_dbi = kirin_pcie_write_dbi,
.link_up = kirin_pcie_link_up,