mirror of https://gitee.com/openkylin/linux.git
drm/amd/display: Initial documentation for AMDgpu DC
[Why] Documentation is helpful for the community to understand our code. This change does some high-level documentation of some DM interfaces with DRM, and the amdgpu base driver. [How] An entry for AMDgpu DC has been added to Documentation/gpu/drivers.rst TOC. amdgpu-dc.rst is created to pull in inline doc-strings, which: - Provides an overview for "What is DM?" - Documents AMDgpu DM lifecyle - Documents IRQ management - Documents atomic_check and commit_tail interfaces Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leo Li
Alex Deucher
parent
4f7129112c
commit
b8592b4845
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@ -0,0 +1,68 @@
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===================================
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drm/amd/display - Display Core (DC)
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===================================
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*placeholder - general description of supported platforms, what dc is, etc.*
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Because it is partially shared with other operating systems, the Display Core
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Driver is divided in two pieces.
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1. **Display Core (DC)** contains the OS-agnostic components. Things like
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hardware programming and resource management are handled here.
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2. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
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amdgpu base driver and DRM are implemented here.
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It doesn't help that the entire package is frequently referred to as DC. But
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with the context in mind, it should be clear.
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When CONFIG_DRM_AMD_DC is enabled, DC will be initialized by default for
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supported ASICs. To force disable, set `amdgpu.dc=0` on kernel command line.
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Likewise, to force enable on unsupported ASICs, set `amdgpu.dc=1`.
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To determine if DC is loaded, search dmesg for the following entry:
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``Display Core initialized with <version number here>``
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AMDgpu Display Manager
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======================
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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:doc: overview
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
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:internal:
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Lifecycle
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---------
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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:doc: DM Lifecycle
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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:functions: dm_hw_init dm_hw_fini
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Interrupts
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----------
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
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:doc: overview
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
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:internal:
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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:functions: register_hpd_handlers dm_crtc_high_irq dm_pflip_high_irq
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Atomic Implementation
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---------------------
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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:doc: atomic
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.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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:functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
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Display Core
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============
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**WIP**
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@ -5,6 +5,7 @@ GPU Driver Documentation
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.. toctree::
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amdgpu
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amdgpu-dc
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i915
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meson
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pl111
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@ -76,6 +76,16 @@
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#define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
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MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
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/**
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* DOC: overview
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*
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* The AMDgpu display manager, **amdgpu_dm** (or even simpler,
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* **dm**) sits between DRM and DC. It acts as a liason, converting DRM
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* requests into DC requests, and DC responses into DRM responses.
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*
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* The root control structure is &struct amdgpu_display_manager.
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*/
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/* basic init/fini API */
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static int amdgpu_dm_init(struct amdgpu_device *adev);
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static void amdgpu_dm_fini(struct amdgpu_device *adev);
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@ -379,11 +389,6 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector)
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}
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/*
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* Init display KMS
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*
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* Returns 0 on success
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*/
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static int amdgpu_dm_init(struct amdgpu_device *adev)
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{
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struct dc_init_data init_data;
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@ -660,6 +665,26 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend)
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drm_modeset_unlock(&dev->mode_config.connection_mutex);
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}
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/**
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* dm_hw_init() - Initialize DC device
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* @handle: The base driver device containing the amdpgu_dm device.
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*
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* Initialize the &struct amdgpu_display_manager device. This involves calling
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* the initializers of each DM component, then populating the struct with them.
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*
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* Although the function implies hardware initialization, both hardware and
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* software are initialized here. Splitting them out to their relevant init
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* hooks is a future TODO item.
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*
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* Some notable things that are initialized here:
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*
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* - Display Core, both software and hardware
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* - DC modules that we need (freesync and color management)
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* - DRM software states
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* - Interrupt sources and handlers
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* - Vblank support
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* - Debug FS entries, if enabled
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*/
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static int dm_hw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@ -670,6 +695,14 @@ static int dm_hw_init(void *handle)
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return 0;
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}
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/**
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* dm_hw_fini() - Teardown DC device
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* @handle: The base driver device containing the amdpgu_dm device.
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*
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* Teardown components within &struct amdgpu_display_manager that require
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* cleanup. This involves cleaning up the DRM device, DC, and any modules that
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* were loaded. Also flush IRQ workqueues and disable them.
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*/
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static int dm_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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@ -895,6 +928,16 @@ static int dm_resume(void *handle)
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return ret;
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}
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/**
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* DOC: DM Lifecycle
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*
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* DM (and consequently DC) is registered in the amdgpu base driver as a IP
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* block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
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* the base driver's device list to be initialized and torn down accordingly.
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*
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* The functions to do so are provided as hooks in &struct amd_ip_funcs.
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*/
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static const struct amd_ip_funcs amdgpu_dm_funcs = {
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.name = "dm",
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.early_init = dm_early_init,
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@ -962,6 +1005,12 @@ dm_atomic_state_alloc_free(struct drm_atomic_state *state)
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kfree(dm_state);
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}
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/**
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* DOC: atomic
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*
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* *WIP*
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*/
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static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
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.fb_create = amdgpu_display_user_framebuffer_create,
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.output_poll_changed = drm_fb_helper_output_poll_changed,
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@ -4542,6 +4591,14 @@ static int amdgpu_dm_atomic_commit(struct drm_device *dev,
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/*TODO Handle EINTR, reenable IRQ*/
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}
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/**
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* amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
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* @state: The atomic state to commit
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*
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* This will tell DC to commit the constructed DC state from atomic_check,
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* programming the hardware. Any failures here implies a hardware failure, since
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* atomic check should have filtered anything non-kosher.
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*/
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static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
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{
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struct drm_device *dev = state->dev;
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@ -5394,6 +5451,31 @@ enum surface_update_type dm_determine_update_type_for_commit(struct dc *dc, stru
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return update_type;
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}
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/**
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* amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
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* @dev: The DRM device
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* @state: The atomic state to commit
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*
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* Validate that the given atomic state is programmable by DC into hardware.
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* This involves constructing a &struct dc_state reflecting the new hardware
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* state we wish to commit, then querying DC to see if it is programmable. It's
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* important not to modify the existing DC state. Otherwise, atomic_check
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* may unexpectedly commit hardware changes.
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*
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* When validating the DC state, it's important that the right locks are
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* acquired. For full updates case which removes/adds/updates streams on one
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* CRTC while flipping on another CRTC, acquiring global lock will guarantee
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* that any such full update commit will wait for completion of any outstanding
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* flip using DRMs synchronization events. See
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* dm_determine_update_type_for_commit()
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*
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* Note that DM adds the affected connectors for all CRTCs in state, when that
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* might not seem necessary. This is because DC stream creation requires the
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* DC sink, which is tied to the DRM connector state. Cleaning this up should
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* be possible but non-trivial - a possible TODO item.
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*
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* Return: -Error code if validation failed.
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*/
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static int amdgpu_dm_atomic_check(struct drm_device *dev,
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struct drm_atomic_state *state)
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{
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@ -5496,15 +5578,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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lock_and_validation_needed = true;
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}
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/*
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* For full updates case when
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* removing/adding/updating streams on one CRTC while flipping
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* on another CRTC,
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* acquiring global lock will guarantee that any such full
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* update commit
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* will wait for completion of any outstanding flip using DRMs
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* synchronization events.
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*/
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update_type = dm_determine_update_type_for_commit(dc, state);
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if (overall_update_type < update_type)
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@ -59,49 +59,100 @@ struct common_irq_params {
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enum dc_irq_source irq_src;
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};
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/**
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* struct irq_list_head - Linked-list for low context IRQ handlers.
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*
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* @head: The list_head within &struct handler_data
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* @work: A work_struct containing the deferred handler work
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*/
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struct irq_list_head {
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struct list_head head;
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/* In case this interrupt needs post-processing, 'work' will be queued*/
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struct work_struct work;
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};
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/**
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* struct dm_compressor_info - Buffer info used by frame buffer compression
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* @cpu_addr: MMIO cpu addr
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* @bo_ptr: Pointer to the buffer object
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* @gpu_addr: MMIO gpu addr
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*/
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struct dm_comressor_info {
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void *cpu_addr;
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struct amdgpu_bo *bo_ptr;
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uint64_t gpu_addr;
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};
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/**
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* struct amdgpu_display_manager - Central amdgpu display manager device
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*
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* @dc: Display Core control structure
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* @adev: AMDGPU base driver structure
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* @ddev: DRM base driver structure
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* @display_indexes_num: Max number of display streams supported
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* @irq_handler_list_table_lock: Synchronizes access to IRQ tables
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* @backlight_dev: Backlight control device
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* @cached_state: Caches device atomic state for suspend/resume
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* @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
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*/
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struct amdgpu_display_manager {
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struct dc *dc;
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/**
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* @cgs_device:
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*
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* The Common Graphics Services device. It provides an interface for
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* accessing registers.
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*/
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struct cgs_device *cgs_device;
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struct amdgpu_device *adev; /*AMD base driver*/
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struct drm_device *ddev; /*DRM base driver*/
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struct amdgpu_device *adev;
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struct drm_device *ddev;
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u16 display_indexes_num;
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/*
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* 'irq_source_handler_table' holds a list of handlers
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* per (DAL) IRQ source.
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/**
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* @irq_handler_list_low_tab:
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*
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* Each IRQ source may need to be handled at different contexts.
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* By 'context' we mean, for example:
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* - The ISR context, which is the direct interrupt handler.
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* - The 'deferred' context - this is the post-processing of the
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* interrupt, but at a lower priority.
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* Low priority IRQ handler table.
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*
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* It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
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* source. Low priority IRQ handlers are deferred to a workqueue to be
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* processed. Hence, they can sleep.
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*
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* Note that handlers are called in the same order as they were
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* registered (FIFO).
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*/
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struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
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/**
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* @irq_handler_list_high_tab:
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*
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* High priority IRQ handler table.
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*
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* It is a n*m table, same as &irq_handler_list_low_tab. However,
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* handlers in this table are not deferred and are called immediately.
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*/
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struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
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/**
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* @pflip_params:
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*
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* Page flip IRQ parameters, passed to registered handlers when
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* triggered.
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*/
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struct common_irq_params
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pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
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/**
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* @vblank_params:
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*
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* Vertical blanking IRQ parameters, passed to registered handlers when
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* triggered.
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*/
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struct common_irq_params
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vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
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/* this spin lock synchronizes access to 'irq_handler_list_table' */
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spinlock_t irq_handler_list_table_lock;
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struct backlight_device *backlight_dev;
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@ -110,9 +161,6 @@ struct amdgpu_display_manager {
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struct mod_freesync *freesync_module;
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/**
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* Caches device atomic state for suspend/resume
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*/
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struct drm_atomic_state *cached_state;
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struct dm_comressor_info compressor;
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@ -32,16 +32,55 @@
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#include "amdgpu_dm.h"
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#include "amdgpu_dm_irq.h"
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/**
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* DOC: overview
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*
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* DM provides another layer of IRQ management on top of what the base driver
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* already provides. This is something that could be cleaned up, and is a
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* future TODO item.
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*
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* The base driver provides IRQ source registration with DRM, handler
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* registration into the base driver's IRQ table, and a handler callback
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* amdgpu_irq_handler(), with which DRM calls on interrupts. This generic
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* handler looks up the IRQ table, and calls the respective
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* &amdgpu_irq_src_funcs.process hookups.
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*
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* What DM provides on top are two IRQ tables specifically for top-half and
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* bottom-half IRQ handling, with the bottom-half implementing workqueues:
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*
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* - &amdgpu_display_manager.irq_handler_list_high_tab
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* - &amdgpu_display_manager.irq_handler_list_low_tab
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*
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* They override the base driver's IRQ table, and the effect can be seen
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* in the hooks that DM provides for &amdgpu_irq_src_funcs.process. They
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* are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up
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* DM's IRQ tables. However, in order for base driver to recognize this hook, DM
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* still needs to register the IRQ with the base driver. See
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* dce110_register_irq_handlers() and dcn10_register_irq_handlers().
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*
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* To expose DC's hardware interrupt toggle to the base driver, DM implements
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* &amdgpu_irq_src_funcs.set hooks. Base driver calls it through
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* amdgpu_irq_update() to enable or disable the interrupt.
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*/
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/******************************************************************************
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* Private declarations.
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*****************************************************************************/
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/**
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* struct amdgpu_dm_irq_handler_data - Data for DM interrupt handlers.
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*
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* @list: Linked list entry referencing the next/previous handler
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* @handler: Handler function
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* @handler_arg: Argument passed to the handler when triggered
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* @dm: DM which this handler belongs to
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* @irq_source: DC interrupt source that this handler is registered for
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*/
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struct amdgpu_dm_irq_handler_data {
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struct list_head list;
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interrupt_handler handler;
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void *handler_arg;
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/* DM which this handler belongs to */
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struct amdgpu_display_manager *dm;
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/* DAL irq source which registered for this interrupt. */
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enum dc_irq_source irq_source;
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@ -68,7 +107,7 @@ static void init_handler_common_data(struct amdgpu_dm_irq_handler_data *hcd,
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}
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/**
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* dm_irq_work_func - Handle an IRQ outside of the interrupt handler proper.
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* dm_irq_work_func() - Handle an IRQ outside of the interrupt handler proper.
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*
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* @work: work struct
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*/
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@ -99,8 +138,8 @@ static void dm_irq_work_func(struct work_struct *work)
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* (The most common use is HPD interrupt) */
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}
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/**
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* Remove a handler and return a pointer to hander list from which the
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/*
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* Remove a handler and return a pointer to handler list from which the
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* handler was removed.
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*/
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static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
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@ -203,6 +242,24 @@ static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
|
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* Note: caller is responsible for input validation.
|
||||
*****************************************************************************/
|
||||
|
||||
/**
|
||||
* amdgpu_dm_irq_register_interrupt() - Register a handler within DM.
|
||||
* @adev: The base driver device containing the DM device.
|
||||
* @int_params: Interrupt parameters containing the source, and handler context
|
||||
* @ih: Function pointer to the interrupt handler to register
|
||||
* @handler_args: Arguments passed to the handler when the interrupt occurs
|
||||
*
|
||||
* Register an interrupt handler for the given IRQ source, under the given
|
||||
* context. The context can either be high or low. High context handlers are
|
||||
* executed directly within ISR context, while low context is executed within a
|
||||
* workqueue, thereby allowing operations that sleep.
|
||||
*
|
||||
* Registered handlers are called in a FIFO manner, i.e. the most recently
|
||||
* registered handler will be called first.
|
||||
*
|
||||
* Return: Handler data &struct amdgpu_dm_irq_handler_data containing the IRQ
|
||||
* source, handler function, and args
|
||||
*/
|
||||
void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
|
||||
struct dc_interrupt_params *int_params,
|
||||
void (*ih)(void *),
|
||||
|
|
@ -261,6 +318,15 @@ void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
|
|||
return handler_data;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_dm_irq_unregister_interrupt() - Remove a handler from the DM IRQ table
|
||||
* @adev: The base driver device containing the DM device
|
||||
* @irq_source: IRQ source to remove the given handler from
|
||||
* @ih: Function pointer to the interrupt handler to unregister
|
||||
*
|
||||
* Go through both low and high context IRQ tables, and find the given handler
|
||||
* for the given irq source. If found, remove it. Otherwise, do nothing.
|
||||
*/
|
||||
void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
|
||||
enum dc_irq_source irq_source,
|
||||
void *ih)
|
||||
|
|
@ -295,6 +361,20 @@ void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_dm_irq_init() - Initialize DM IRQ management
|
||||
* @adev: The base driver device containing the DM device
|
||||
*
|
||||
* Initialize DM's high and low context IRQ tables.
|
||||
*
|
||||
* The N by M table contains N IRQ sources, with M
|
||||
* &struct amdgpu_dm_irq_handler_data hooked together in a linked list. The
|
||||
* list_heads are initialized here. When an interrupt n is triggered, all m
|
||||
* handlers are called in sequence, FIFO according to registration order.
|
||||
*
|
||||
* The low context table requires special steps to initialize, since handlers
|
||||
* will be deferred to a workqueue. See &struct irq_list_head.
|
||||
*/
|
||||
int amdgpu_dm_irq_init(struct amdgpu_device *adev)
|
||||
{
|
||||
int src;
|
||||
|
|
@ -317,7 +397,12 @@ int amdgpu_dm_irq_init(struct amdgpu_device *adev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* DM IRQ and timer resource release */
|
||||
/**
|
||||
* amdgpu_dm_irq_fini() - Tear down DM IRQ management
|
||||
* @adev: The base driver device containing the DM device
|
||||
*
|
||||
* Flush all work within the low context IRQ table.
|
||||
*/
|
||||
void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
|
||||
{
|
||||
int src;
|
||||
|
|
@ -414,7 +499,7 @@ int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
/*
|
||||
* amdgpu_dm_irq_schedule_work - schedule all work items registered for the
|
||||
* "irq_source".
|
||||
*/
|
||||
|
|
@ -439,8 +524,9 @@ static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
|
|||
|
||||
}
|
||||
|
||||
/** amdgpu_dm_irq_immediate_work
|
||||
* Callback high irq work immediately, don't send to work queue
|
||||
/*
|
||||
* amdgpu_dm_irq_immediate_work
|
||||
* Callback high irq work immediately, don't send to work queue
|
||||
*/
|
||||
static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
|
||||
enum dc_irq_source irq_source)
|
||||
|
|
@ -467,11 +553,14 @@ static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
|
|||
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* amdgpu_dm_irq_handler
|
||||
/**
|
||||
* amdgpu_dm_irq_handler - Generic DM IRQ handler
|
||||
* @adev: amdgpu base driver device containing the DM device
|
||||
* @source: Unused
|
||||
* @entry: Data about the triggered interrupt
|
||||
*
|
||||
* Generic IRQ handler, calls all registered high irq work immediately, and
|
||||
* schedules work for low irq
|
||||
* Calls all registered high irq work immediately, and schedules work for low
|
||||
* irq. The DM IRQ table is used to find the corresponding handlers.
|
||||
*/
|
||||
static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
|
||||
struct amdgpu_irq_src *source,
|
||||
|
|
@ -613,7 +702,7 @@ void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
|
|||
adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
|
||||
}
|
||||
|
||||
/*
|
||||
/**
|
||||
* amdgpu_dm_hpd_init - hpd setup callback.
|
||||
*
|
||||
* @adev: amdgpu_device pointer
|
||||
|
|
|
|||
Loading…
Reference in New Issue