mirror of https://gitee.com/openkylin/linux.git
Merge branch 'mvpp2-fixes'
Thomas Petazzoni says: ==================== net: mvpp2: driver fixes As requested, here is a series of patches containing only bug fixes for the mvpp2 driver. It is based on the latest "net" branch. Changes since v1: - Fixed a build breakage that occurred when only PATCH 1 was only, and not later patches in the series. Was reported by the kbuild report on the first submission. - Added Tested-by from Marc Zyngier on PATCH 2. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
b87fa0fafe
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@ -3719,7 +3719,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
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dma_addr_t *dma_addr,
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phys_addr_t *phys_addr)
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{
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int cpu = smp_processor_id();
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int cpu = get_cpu();
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*dma_addr = mvpp2_percpu_read(priv, cpu,
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MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
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@ -3740,6 +3740,8 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
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if (sizeof(phys_addr_t) == 8)
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*phys_addr |= (u64)phys_addr_highbits << 32;
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}
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put_cpu();
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}
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/* Free all buffers from the pool */
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@ -3920,18 +3922,12 @@ static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
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return bm;
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}
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/* Get pool number from a BM cookie */
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static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
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{
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return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
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}
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/* Release buffer to BM */
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static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
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dma_addr_t buf_dma_addr,
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phys_addr_t buf_phys_addr)
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{
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int cpu = smp_processor_id();
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int cpu = get_cpu();
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if (port->priv->hw_version == MVPP22) {
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u32 val = 0;
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@ -3958,15 +3954,15 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
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MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
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mvpp2_percpu_write(port->priv, cpu,
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MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
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put_cpu();
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}
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/* Refill BM pool */
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static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
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static void mvpp2_pool_refill(struct mvpp2_port *port, int pool,
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dma_addr_t dma_addr,
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phys_addr_t phys_addr)
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{
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int pool = mvpp2_bm_cookie_pool_get(bm);
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mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
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}
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@ -4513,21 +4509,6 @@ static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
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mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
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}
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/* Obtain BM cookie information from descriptor */
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static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
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struct mvpp2_rx_desc *rx_desc)
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{
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int cpu = smp_processor_id();
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int pool;
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pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
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MVPP2_RXD_BM_POOL_ID_MASK) >>
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MVPP2_RXD_BM_POOL_ID_OFFS;
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return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
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((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
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}
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/* Tx descriptors helper methods */
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/* Get pointer to next Tx descriptor to be processed (send) by HW */
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@ -4755,7 +4736,7 @@ static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
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static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
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struct mvpp2_rx_queue *rxq)
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{
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int cpu = smp_processor_id();
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int cpu = get_cpu();
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if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
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rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
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@ -4763,6 +4744,8 @@ static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_THRESH_REG,
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rxq->pkts_coal);
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put_cpu();
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}
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static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
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@ -4943,7 +4926,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
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mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
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/* Set Rx descriptors queue starting address - indirect access */
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cpu = smp_processor_id();
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cpu = get_cpu();
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
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if (port->priv->hw_version == MVPP21)
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rxq_dma = rxq->descs_dma;
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@ -4952,6 +4935,7 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_INDEX_REG, 0);
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put_cpu();
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/* Set Offset */
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mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
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@ -4978,9 +4962,13 @@ static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
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for (i = 0; i < rx_received; i++) {
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struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
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u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
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u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
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int pool;
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mvpp2_pool_refill(port, bm,
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pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
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MVPP2_RXD_BM_POOL_ID_OFFS;
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mvpp2_pool_refill(port, pool,
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mvpp2_rxdesc_dma_addr_get(port, rx_desc),
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mvpp2_rxdesc_cookie_get(port, rx_desc));
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}
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@ -5010,10 +4998,11 @@ static void mvpp2_rxq_deinit(struct mvpp2_port *port,
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* free descriptor number
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*/
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mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
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cpu = smp_processor_id();
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cpu = get_cpu();
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_NUM_REG, rxq->id);
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_ADDR_REG, 0);
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mvpp2_percpu_write(port->priv, cpu, MVPP2_RXQ_DESC_SIZE_REG, 0);
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put_cpu();
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}
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/* Create and initialize a Tx queue */
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@ -5036,7 +5025,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
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txq->last_desc = txq->size - 1;
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/* Set Tx descriptors queue starting address - indirect access */
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cpu = smp_processor_id();
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cpu = get_cpu();
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mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
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mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG,
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txq->descs_dma);
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@ -5061,6 +5050,7 @@ static int mvpp2_txq_init(struct mvpp2_port *port,
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mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG,
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MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
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MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
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put_cpu();
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/* WRR / EJP configuration - indirect access */
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tx_port_num = mvpp2_egress_port(port);
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@ -5131,10 +5121,11 @@ static void mvpp2_txq_deinit(struct mvpp2_port *port,
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mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
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/* Set Tx descriptors queue starting address and size */
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cpu = smp_processor_id();
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cpu = get_cpu();
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mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
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mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_ADDR_REG, 0);
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mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_DESC_SIZE_REG, 0);
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put_cpu();
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}
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/* Cleanup Tx ports */
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@ -5144,7 +5135,7 @@ static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
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int delay, pending, cpu;
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u32 val;
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cpu = smp_processor_id();
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cpu = get_cpu();
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mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_NUM_REG, txq->id);
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val = mvpp2_percpu_read(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG);
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val |= MVPP2_TXQ_DRAIN_EN_MASK;
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@ -5171,6 +5162,7 @@ static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
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val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
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mvpp2_percpu_write(port->priv, cpu, MVPP2_TXQ_PREF_BUF_REG, val);
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put_cpu();
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for_each_present_cpu(cpu) {
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txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
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@ -5418,7 +5410,7 @@ static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
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/* Reuse skb if possible, or allocate a new skb and add it to BM pool */
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static int mvpp2_rx_refill(struct mvpp2_port *port,
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struct mvpp2_bm_pool *bm_pool, u32 bm)
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struct mvpp2_bm_pool *bm_pool, int pool)
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{
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dma_addr_t dma_addr;
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phys_addr_t phys_addr;
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@ -5430,7 +5422,7 @@ static int mvpp2_rx_refill(struct mvpp2_port *port,
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if (!buf)
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return -ENOMEM;
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mvpp2_pool_refill(port, bm, dma_addr, phys_addr);
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mvpp2_pool_refill(port, pool, dma_addr, phys_addr);
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return 0;
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}
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@ -5488,7 +5480,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
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unsigned int frag_size;
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dma_addr_t dma_addr;
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phys_addr_t phys_addr;
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u32 bm, rx_status;
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u32 rx_status;
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int pool, rx_bytes, err;
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void *data;
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@ -5500,8 +5492,8 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
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phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
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data = (void *)phys_to_virt(phys_addr);
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bm = mvpp2_bm_cookie_build(port, rx_desc);
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pool = mvpp2_bm_cookie_pool_get(bm);
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pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
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MVPP2_RXD_BM_POOL_ID_OFFS;
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bm_pool = &port->priv->bm_pools[pool];
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/* In case of an error, release the requested buffer pointer
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@ -5514,7 +5506,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
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dev->stats.rx_errors++;
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mvpp2_rx_error(port, rx_desc);
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/* Return the buffer to the pool */
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mvpp2_pool_refill(port, bm, dma_addr, phys_addr);
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mvpp2_pool_refill(port, pool, dma_addr, phys_addr);
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continue;
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}
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@ -5529,7 +5521,7 @@ static int mvpp2_rx(struct mvpp2_port *port, int rx_todo,
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goto err_drop_frame;
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}
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err = mvpp2_rx_refill(port, bm_pool, bm);
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err = mvpp2_rx_refill(port, bm_pool, pool);
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if (err) {
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netdev_err(port->dev, "failed to refill BM pools\n");
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goto err_drop_frame;
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