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usb: dwc2: Reorder AHBIDLE and CSFTRST in dwc2_core_reset() 

According to the databook, the core soft reset should be done before
checking for AHBIDLE. The gadget version of core reset had it correct
but the hcd version did not. This fixes the hcd version.

Signed-off-by: John Youn <johnyoun@synopsys.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
John Youn 2015-12-17 11:15:35 -08:00 committed by Felipe Balbi
parent 7d56cc2620
commit b8ccc593ee
1 changed files with 14 additions and 13 deletions
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27
drivers/usb/dwc2/core.c
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@ -489,20 +489,8 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg)
dev_vdbg(hsotg->dev, "%s()\n", __func__); dev_vdbg(hsotg->dev, "%s()\n", __func__);
/* Wait for AHB master IDLE state */
do {
udelay(1);
greset = dwc2_readl(hsotg->regs + GRSTCTL);
if (++count > 50) {
dev_warn(hsotg->dev,
"%s() HANG! AHB Idle GRSTCTL=%0x\n",
__func__, greset);
return -EBUSY;
}
} while (!(greset & GRSTCTL_AHBIDLE));
/* Core Soft Reset */ /* Core Soft Reset */
count = 0; greset = dwc2_readl(hsotg->regs + GRSTCTL);
greset |= GRSTCTL_CSFTRST; greset |= GRSTCTL_CSFTRST;
dwc2_writel(greset, hsotg->regs + GRSTCTL); dwc2_writel(greset, hsotg->regs + GRSTCTL);
do { do {
@ -516,6 +504,19 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg)
} }
} while (greset & GRSTCTL_CSFTRST); } while (greset & GRSTCTL_CSFTRST);
/* Wait for AHB master IDLE state */
count = 0;
do {
udelay(1);
greset = dwc2_readl(hsotg->regs + GRSTCTL);
if (++count > 50) {
dev_warn(hsotg->dev,
"%s() HANG! AHB Idle GRSTCTL=%0x\n",
__func__, greset);
return -EBUSY;
}
} while (!(greset & GRSTCTL_AHBIDLE));
if (hsotg->dr_mode == USB_DR_MODE_HOST) { if (hsotg->dr_mode == USB_DR_MODE_HOST) {
gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
gusbcfg &= ~GUSBCFG_FORCEDEVMODE; gusbcfg &= ~GUSBCFG_FORCEDEVMODE;