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PCI: mvebu: Avoid changing the SCC bit in the Link Status register 

It seems on later Armada 38x, the slot clock configuration bit is not
read-only, but can be written.  This means that our RW1C protection ends up
clearing this bit when the link control register is written.

Adjust the mask so that we only avoid writing '1' bits to the RW1C bits of
this register (bits 15 and 14 of the link status) rather than masking out
all the status register bits.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Russell King 2017-01-17 21:40:52 +00:00 committed by Bjorn Helgaas
parent c1ae3cfa0e
commit b8e82c1bdd
1 changed files with 3 additions and 2 deletions
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5
drivers/pci/host/pci-mvebu.c
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@ -752,10 +752,11 @@ static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
* If the mask is 0xffff0000, then we only want to write
* the link control register, rather than clearing the
* RW1C bits in the link status register. Mask out the
* status register bits.
* RW1C status register bits.
*/
if (mask == 0xffff0000)
value &= 0xffff;
value &= ~((PCI_EXP_LNKSTA_LABS |
PCI_EXP_LNKSTA_LBMS) << 16);
mvebu_writel(port, value, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
break;