mirror of https://gitee.com/openkylin/linux.git
[MIPS] R2 bitops compile fix for gcc < 4.0.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
a5664c4075
commit
b961153be9
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@ -54,6 +54,7 @@
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static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned short bit = nr & SZLONG_MASK;
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unsigned long temp;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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@ -65,9 +66,9 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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: "ir" (1UL << bit), "m" (*m));
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#ifdef CONFIG_CPU_MIPSR2
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} else if (__builtin_constant_p(nr)) {
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} else if (__builtin_constant_p(bit)) {
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # set_bit \n"
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" " __INS "%0, %4, %2, 1 \n"
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@ -77,7 +78,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (nr & SZLONG_MASK), "m" (*m), "r" (~0));
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: "ir" (bit), "m" (*m), "r" (~0));
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#endif /* CONFIG_CPU_MIPSR2 */
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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@ -91,14 +92,14 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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" .previous \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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: "ir" (1UL << bit), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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mask = 1UL << bit;
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local_irq_save(flags);
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*a |= mask;
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local_irq_restore(flags);
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@ -118,6 +119,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned short bit = nr & SZLONG_MASK;
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unsigned long temp;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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@ -129,9 +131,9 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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: "ir" (~(1UL << bit)), "m" (*m));
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#ifdef CONFIG_CPU_MIPSR2
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} else if (__builtin_constant_p(nr)) {
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} else if (__builtin_constant_p(bit)) {
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__asm__ __volatile__(
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"1: " __LL "%0, %1 # clear_bit \n"
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" " __INS "%0, $0, %2, 1 \n"
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@ -141,7 +143,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (nr & SZLONG_MASK), "m" (*m));
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: "ir" (bit), "m" (*m));
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#endif /* CONFIG_CPU_MIPSR2 */
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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@ -155,14 +157,14 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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" .previous \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
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: "ir" (~(1UL << bit)), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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mask = 1UL << bit;
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local_irq_save(flags);
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*a &= ~mask;
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local_irq_restore(flags);
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@ -180,6 +182,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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*/
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static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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@ -192,7 +196,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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: "ir" (1UL << bit), "m" (*m));
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} else if (cpu_has_llsc) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp;
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@ -208,14 +212,14 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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" .previous \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m)
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: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
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: "ir" (1UL << bit), "m" (*m));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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mask = 1UL << bit;
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local_irq_save(flags);
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*a ^= mask;
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local_irq_restore(flags);
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@ -233,6 +237,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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static inline int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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@ -246,7 +252,7 @@ static inline int test_and_set_bit(unsigned long nr,
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" and %2, %0, %3 \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "r" (1UL << bit), "m" (*m)
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: "memory");
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return res != 0;
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@ -269,7 +275,7 @@ static inline int test_and_set_bit(unsigned long nr,
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" .previous \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "r" (1UL << bit), "m" (*m)
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: "memory");
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return res != 0;
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@ -280,7 +286,7 @@ static inline int test_and_set_bit(unsigned long nr,
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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mask = 1UL << bit;
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local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a |= mask;
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@ -303,6 +309,8 @@ static inline int test_and_set_bit(unsigned long nr,
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static inline int test_and_clear_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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@ -317,7 +325,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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" and %2, %0, %3 \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "r" (1UL << bit), "m" (*m)
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: "memory");
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return res != 0;
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@ -336,7 +344,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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"2: b 1b \n"
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" .previous \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "ri" (nr & SZLONG_MASK), "m" (*m)
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: "ri" (bit), "m" (*m)
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: "memory");
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return res;
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@ -361,7 +369,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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" .previous \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "r" (1UL << bit), "m" (*m)
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: "memory");
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return res != 0;
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@ -372,7 +380,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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mask = 1UL << bit;
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local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a &= ~mask;
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@ -395,6 +403,8 @@ static inline int test_and_clear_bit(unsigned long nr,
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static inline int test_and_change_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned long temp, res;
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@ -408,7 +418,7 @@ static inline int test_and_change_bit(unsigned long nr,
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" and %2, %0, %3 \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "r" (1UL << bit), "m" (*m)
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: "memory");
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return res != 0;
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@ -431,7 +441,7 @@ static inline int test_and_change_bit(unsigned long nr,
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" .previous \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*m), "=&r" (res)
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: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
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: "r" (1UL << bit), "m" (*m)
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: "memory");
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return res != 0;
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@ -441,7 +451,7 @@ static inline int test_and_change_bit(unsigned long nr,
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << (nr & SZLONG_MASK);
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mask = 1UL << bit;
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local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a ^= mask;
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