mirror of https://gitee.com/openkylin/linux.git
powerpc/32: Replace ASM exception exit by C exception exit from ppc64
This patch replaces the PPC32 ASM exception exit by C exception exit. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/48f8bae91da899d8e73fc0d75c9af66cc97b4d5b.1615552867.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy
Michael Ellerman
parent
e9f99704aa
commit
b96bae3ae2
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@ -336,7 +336,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPE)
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fast_exception_return:
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
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andi. r10,r9,MSR_RI /* check for recoverable interrupt */
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beq 1f /* if not, we've got problems */
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beq 3f /* if not, we've got problems */
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#endif
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2: REST_4GPRS(3, r11)
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@ -363,30 +363,6 @@ fast_exception_return:
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#endif
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_ASM_NOKPROBE_SYMBOL(fast_exception_return)
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
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/* check if the exception happened in a restartable section */
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1: lis r3,exc_exit_restart_end@ha
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addi r3,r3,exc_exit_restart_end@l
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cmplw r12,r3
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bge 3f
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lis r4,exc_exit_restart@ha
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addi r4,r4,exc_exit_restart@l
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cmplw r12,r4
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blt 3f
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lis r3,fee_restarts@ha
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tophys(r3,r3)
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lwz r5,fee_restarts@l(r3)
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addi r5,r5,1
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stw r5,fee_restarts@l(r3)
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mr r12,r4 /* restart at exc_exit_restart */
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b 2b
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.section .bss
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.align 2
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fee_restarts:
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.space 4
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.previous
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/* aargh, a nonrecoverable interrupt, panic */
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/* aargh, we don't know which trap this is */
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3:
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@ -395,8 +371,7 @@ fee_restarts:
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl transfer_to_handler_full
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bl unrecoverable_exception
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b ret_from_except
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#endif
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trap /* should not get here */
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.globl ret_from_except_full
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ret_from_except_full:
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@ -405,213 +380,145 @@ ret_from_except_full:
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.globl ret_from_except
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ret_from_except:
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/* Hard-disable interrupts so that current_thread_info()->flags
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* can't change between when we test it and when we return
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* from the interrupt. */
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/* Note: We don't bother telling lockdep about it */
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
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mtmsr r10 /* disable interrupts */
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_ASM_NOKPROBE_SYMBOL(ret_from_except)
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lwz r3,_MSR(r1) /* Returning to user mode? */
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andi. r0,r3,MSR_PR
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beq resume_kernel
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.globl interrupt_return
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interrupt_return:
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lwz r4,_MSR(r1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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andi. r0,r4,MSR_PR
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beq .Lkernel_interrupt_return
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bl interrupt_exit_user_prepare
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cmpwi r3,0
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bne- .Lrestore_nvgprs
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user_exc_return: /* r10 contains MSR_KERNEL here */
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/* Check current_thread_info()->flags */
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lwz r9,TI_FLAGS(r2)
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andi. r0,r9,_TIF_USER_WORK_MASK
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bne do_work
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restore_user:
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#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
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/* Check whether this process has its own DBCR0 value. The internal
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debug mode bit tells us that dbcr0 should be loaded. */
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lwz r0,THREAD+THREAD_DBCR0(r2)
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andis. r10,r0,DBCR0_IDM@h
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bnel- load_dbcr0
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#endif
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ACCOUNT_CPU_USER_EXIT(r2, r10, r11)
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.Lfast_user_interrupt_return:
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#ifdef CONFIG_PPC_BOOK3S_32
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kuep_unlock r10, r11
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#endif
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b restore
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/* N.B. the only way to get here is from the beq following ret_from_except. */
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resume_kernel:
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/* check current_thread_info, _TIF_EMULATE_STACK_STORE */
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lwz r8,TI_FLAGS(r2)
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andis. r0,r8,_TIF_EMULATE_STACK_STORE@h
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beq+ 1f
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addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */
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lwz r3,GPR1(r1)
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subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */
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mr r4,r1 /* src: current exception frame */
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mr r1,r3 /* Reroute the trampoline frame to r1 */
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/* Copy from the original to the trampoline. */
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li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */
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li r6,0 /* start offset: 0 */
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mtctr r5
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2: lwzx r0,r6,r4
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stwx r0,r6,r3
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addi r6,r6,4
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bdnz 2b
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/* Do real store operation to complete stwu */
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lwz r5,GPR1(r1)
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stw r8,0(r5)
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/* Clear _TIF_EMULATE_STACK_STORE flag */
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lis r11,_TIF_EMULATE_STACK_STORE@h
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addi r5,r2,TI_FLAGS
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0: lwarx r8,0,r5
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andc r8,r8,r11
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stwcx. r8,0,r5
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bne- 0b
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1:
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#ifdef CONFIG_PREEMPTION
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/* check current_thread_info->preempt_count */
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lwz r0,TI_PREEMPT(r2)
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cmpwi 0,r0,0 /* if non-zero, just restore regs and return */
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bne restore_kuap
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andi. r8,r8,_TIF_NEED_RESCHED
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beq+ restore_kuap
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lwz r3,_MSR(r1)
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andi. r0,r3,MSR_EE /* interrupts off? */
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beq restore_kuap /* don't schedule if so */
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#ifdef CONFIG_TRACE_IRQFLAGS
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/* Lockdep thinks irqs are enabled, we need to call
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* preempt_schedule_irq with IRQs off, so we inform lockdep
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* now that we -did- turn them off already
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*/
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bl trace_hardirqs_off
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#endif
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bl preempt_schedule_irq
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#ifdef CONFIG_TRACE_IRQFLAGS
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/* And now, to properly rebalance the above, we tell lockdep they
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* are being turned back on, which will happen when we return
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*/
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bl trace_hardirqs_on
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#endif
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#endif /* CONFIG_PREEMPTION */
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restore_kuap:
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kuap_restore r1, r2, r9, r10, r0
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/* interrupts are hard-disabled at this point */
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restore:
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#if defined(CONFIG_44x) && !defined(CONFIG_PPC_47x)
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lis r4,icache_44x_need_flush@ha
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lwz r5,icache_44x_need_flush@l(r4)
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cmplwi cr0,r5,0
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beq+ 1f
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li r6,0
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iccci r0,r0
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stw r6,icache_44x_need_flush@l(r4)
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1:
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#endif /* CONFIG_44x */
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lwz r9,_MSR(r1)
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#ifdef CONFIG_TRACE_IRQFLAGS
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/* Lockdep doesn't know about the fact that IRQs are temporarily turned
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* off in this assembly code while peeking at TI_FLAGS() and such. However
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* we need to inform it if the exception turned interrupts off, and we
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* are about to trun them back on.
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*/
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andi. r10,r9,MSR_EE
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beq 1f
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stwu r1,-32(r1)
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mflr r0
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stw r0,4(r1)
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bl trace_hardirqs_on
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addi r1, r1, 32
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lwz r9,_MSR(r1)
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1:
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#endif /* CONFIG_TRACE_IRQFLAGS */
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lwz r0,GPR0(r1)
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lwz r2,GPR2(r1)
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REST_4GPRS(3, r1)
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REST_2GPRS(7, r1)
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lwz r10,_XER(r1)
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lwz r11,_CTR(r1)
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mtspr SPRN_XER,r10
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mtctr r11
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BEGIN_FTR_SECTION
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lwarx r11,0,r1
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END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
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stwcx. r0,0,r1 /* to clear the reservation */
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
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andi. r10,r9,MSR_RI /* check if this exception occurred */
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beql nonrecoverable /* at a bad place (MSR:RI = 0) */
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lwz r10,_CCR(r1)
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lwz r11,_LINK(r1)
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mtcrf 0xFF,r10
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mtlr r11
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/* Clear the exception_marker on the stack to avoid confusing stacktrace */
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li r10, 0
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stw r10, 8(r1)
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/*
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* Once we put values in SRR0 and SRR1, we are in a state
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* where exceptions are not recoverable, since taking an
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* exception will trash SRR0 and SRR1. Therefore we clear the
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* MSR:RI bit to indicate this. If we do take an exception,
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* we can't return to the point of the exception but we
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* can restart the exception exit path at the label
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* exc_exit_restart below. -- paulus
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*/
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI)
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mtmsr r10 /* clear the RI bit */
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.globl exc_exit_restart
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exc_exit_restart:
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lwz r12,_NIP(r1)
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mtspr SPRN_SRR0,r12
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mtspr SPRN_SRR1,r9
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REST_4GPRS(9, r1)
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lwz r1,GPR1(r1)
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.globl exc_exit_restart_end
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exc_exit_restart_end:
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rfi
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_ASM_NOKPROBE_SYMBOL(exc_exit_restart)
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_ASM_NOKPROBE_SYMBOL(exc_exit_restart_end)
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#else /* !(CONFIG_4xx || CONFIG_BOOKE) */
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/*
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* This is a bit different on 4xx/Book-E because it doesn't have
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* the RI bit in the MSR.
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* The TLB miss handler checks if we have interrupted
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* the exception exit path and restarts it if so
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* (well maybe one day it will... :).
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*/
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lwz r11,_LINK(r1)
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mtlr r11
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lwz r10,_CCR(r1)
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mtcrf 0xff,r10
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/* Clear the exception_marker on the stack to avoid confusing stacktrace */
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li r10, 0
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stw r10, 8(r1)
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REST_2GPRS(9, r1)
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.globl exc_exit_restart
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exc_exit_restart:
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kuap_check r2, r4
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lwz r11,_NIP(r1)
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lwz r12,_MSR(r1)
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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BEGIN_FTR_SECTION
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stwcx. r0,0,r1 /* to clear the reservation */
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FTR_SECTION_ELSE
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lwarx r0,0,r1
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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lwz r3,_CCR(r1)
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lwz r4,_LINK(r1)
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lwz r5,_CTR(r1)
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lwz r6,_XER(r1)
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li r0,0
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/*
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* Leaving a stale exception_marker on the stack can confuse
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* the reliable stack unwinder later on. Clear it.
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*/
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stw r0,8(r1)
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REST_4GPRS(7, r1)
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REST_2GPRS(11, r1)
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lwz r1,GPR1(r1)
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.globl exc_exit_restart_end
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exc_exit_restart_end:
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mtcr r3
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mtlr r4
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mtctr r5
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mtspr SPRN_XER,r6
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REST_4GPRS(2, r1)
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REST_GPR(6, r1)
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REST_GPR(0, r1)
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REST_GPR(1, r1)
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rfi
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b . /* prevent prefetch past rfi */
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_ASM_NOKPROBE_SYMBOL(exc_exit_restart)
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#ifdef CONFIG_40x
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b . /* Prevent prefetch past rfi */
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#endif
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.Lrestore_nvgprs:
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REST_NVGPRS(r1)
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b .Lfast_user_interrupt_return
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.Lkernel_interrupt_return:
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bl interrupt_exit_kernel_prepare
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.Lfast_kernel_interrupt_return:
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cmpwi cr1,r3,0
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kuap_restore r1, r2, r3, r4, r5
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lwz r11,_NIP(r1)
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lwz r12,_MSR(r1)
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mtspr SPRN_SRR0,r11
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mtspr SPRN_SRR1,r12
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BEGIN_FTR_SECTION
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stwcx. r0,0,r1 /* to clear the reservation */
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FTR_SECTION_ELSE
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lwarx r0,0,r1
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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lwz r3,_LINK(r1)
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lwz r4,_CTR(r1)
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lwz r5,_XER(r1)
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lwz r6,_CCR(r1)
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li r0,0
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REST_4GPRS(7, r1)
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REST_2GPRS(11, r1)
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mtlr r3
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mtctr r4
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mtspr SPRN_XER,r5
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/*
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* Leaving a stale exception_marker on the stack can confuse
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* the reliable stack unwinder later on. Clear it.
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*/
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stw r0,8(r1)
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REST_4GPRS(2, r1)
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bne- cr1,1f /* emulate stack store */
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mtcr r6
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REST_GPR(6, r1)
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REST_GPR(0, r1)
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REST_GPR(1, r1)
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rfi
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#ifdef CONFIG_40x
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b . /* Prevent prefetch past rfi */
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#endif
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1: /*
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* Emulate stack store with update. New r1 value was already calculated
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* and updated in our interrupt regs by emulate_loadstore, but we can't
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* store the previous value of r1 to the stack before re-loading our
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* registers from it, otherwise they could be clobbered. Use
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* SPRG Scratch0 as temporary storage to hold the store
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* data, as interrupts are disabled here so it won't be clobbered.
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*/
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mtcr r6
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#ifdef CONFIG_BOOKE
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mtspr SPRN_SPRG_WSCRATCH0, r9
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#else
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mtspr SPRN_SPRG_SCRATCH0, r9
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#endif
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addi r9,r1,INT_FRAME_SIZE /* get original r1 */
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REST_GPR(6, r1)
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REST_GPR(0, r1)
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REST_GPR(1, r1)
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stw r9,0(r1) /* perform store component of stwu */
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#ifdef CONFIG_BOOKE
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mfspr r9, SPRN_SPRG_RSCRATCH0
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#else
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mfspr r9, SPRN_SPRG_SCRATCH0
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#endif
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rfi
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#ifdef CONFIG_40x
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b . /* Prevent prefetch past rfi */
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#endif
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_ASM_NOKPROBE_SYMBOL(interrupt_return)
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#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
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/*
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* Returning from a critical interrupt in user mode doesn't need
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@ -642,8 +549,7 @@ _ASM_NOKPROBE_SYMBOL(exc_exit_restart)
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REST_NVGPRS(r1); \
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lwz r3,_MSR(r1); \
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andi. r3,r3,MSR_PR; \
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LOAD_REG_IMMEDIATE(r10,MSR_KERNEL); \
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bne user_exc_return; \
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bne interrupt_return; \
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lwz r0,GPR0(r1); \
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lwz r2,GPR2(r1); \
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REST_4GPRS(3, r1); \
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@ -746,114 +652,8 @@ ret_from_mcheck_exc:
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RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
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_ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc)
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#endif /* CONFIG_BOOKE */
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/*
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* Load the DBCR0 value for a task that is being ptraced,
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* having first saved away the global DBCR0. Note that r0
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* has the dbcr0 value to set upon entry to this.
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*/
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load_dbcr0:
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mfmsr r10 /* first disable debug exceptions */
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rlwinm r10,r10,0,~MSR_DE
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mtmsr r10
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isync
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mfspr r10,SPRN_DBCR0
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lis r11,global_dbcr0@ha
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addi r11,r11,global_dbcr0@l
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#ifdef CONFIG_SMP
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lwz r9,TASK_CPU(r2)
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slwi r9,r9,2
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add r11,r11,r9
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#endif
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stw r10,0(r11)
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mtspr SPRN_DBCR0,r0
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li r11,-1
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mtspr SPRN_DBSR,r11 /* clear all pending debug events */
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blr
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.section .bss
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.align 4
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||||
.global global_dbcr0
|
||||
global_dbcr0:
|
||||
.space 4*NR_CPUS
|
||||
.previous
|
||||
#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */
|
||||
|
||||
do_work: /* r10 contains MSR_KERNEL here */
|
||||
andi. r0,r9,_TIF_NEED_RESCHED
|
||||
beq do_user_signal
|
||||
|
||||
do_resched: /* r10 contains MSR_KERNEL here */
|
||||
#ifdef CONFIG_TRACE_IRQFLAGS
|
||||
bl trace_hardirqs_on
|
||||
mfmsr r10
|
||||
#endif
|
||||
ori r10,r10,MSR_EE
|
||||
mtmsr r10 /* hard-enable interrupts */
|
||||
bl schedule
|
||||
recheck:
|
||||
/* Note: And we don't tell it we are disabling them again
|
||||
* neither. Those disable/enable cycles used to peek at
|
||||
* TI_FLAGS aren't advertised.
|
||||
*/
|
||||
LOAD_REG_IMMEDIATE(r10,MSR_KERNEL)
|
||||
mtmsr r10 /* disable interrupts */
|
||||
lwz r9,TI_FLAGS(r2)
|
||||
andi. r0,r9,_TIF_NEED_RESCHED
|
||||
bne- do_resched
|
||||
andi. r0,r9,_TIF_USER_WORK_MASK
|
||||
beq restore_user
|
||||
do_user_signal: /* r10 contains MSR_KERNEL here */
|
||||
ori r10,r10,MSR_EE
|
||||
mtmsr r10 /* hard-enable interrupts */
|
||||
2: addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
mr r4,r9
|
||||
bl do_notify_resume
|
||||
REST_NVGPRS(r1)
|
||||
b recheck
|
||||
|
||||
/*
|
||||
* We come here when we are at the end of handling an exception
|
||||
* that occurred at a place where taking an exception will lose
|
||||
* state information, such as the contents of SRR0 and SRR1.
|
||||
*/
|
||||
nonrecoverable:
|
||||
lis r10,exc_exit_restart_end@ha
|
||||
addi r10,r10,exc_exit_restart_end@l
|
||||
cmplw r12,r10
|
||||
bge 3f
|
||||
lis r11,exc_exit_restart@ha
|
||||
addi r11,r11,exc_exit_restart@l
|
||||
cmplw r12,r11
|
||||
blt 3f
|
||||
lis r10,ee_restarts@ha
|
||||
lwz r12,ee_restarts@l(r10)
|
||||
addi r12,r12,1
|
||||
stw r12,ee_restarts@l(r10)
|
||||
mr r12,r11 /* restart at exc_exit_restart */
|
||||
blr
|
||||
3: /* OK, we can't recover, kill this process */
|
||||
lwz r3,_TRAP(r1)
|
||||
andi. r0,r3,1
|
||||
beq 5f
|
||||
SAVE_NVGPRS(r1)
|
||||
rlwinm r3,r3,0,0,30
|
||||
stw r3,_TRAP(r1)
|
||||
5: mfspr r2,SPRN_SPRG_THREAD
|
||||
addi r2,r2,-THREAD
|
||||
tovirt(r2,r2) /* set back r2 to current */
|
||||
4: addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl unrecoverable_exception
|
||||
/* shouldn't return */
|
||||
b 4b
|
||||
_ASM_NOKPROBE_SYMBOL(nonrecoverable)
|
||||
|
||||
.section .bss
|
||||
.align 2
|
||||
ee_restarts:
|
||||
.space 4
|
||||
.previous
|
||||
|
||||
/*
|
||||
* PROM code for specific machines follows. Put it
|
||||
* here so it's easy to add arch-specific sections later.
|
||||
|
|
|
|||
|
|
@ -20,6 +20,10 @@
|
|||
#include <asm/time.h>
|
||||
#include <asm/unistd.h>
|
||||
|
||||
#if defined(CONFIG_PPC_ADV_DEBUG_REGS) && defined(CONFIG_PPC32)
|
||||
unsigned long global_dbcr0[NR_CPUS];
|
||||
#endif
|
||||
|
||||
typedef long (*syscall_fn)(long, long, long, long, long, long);
|
||||
|
||||
/* Has to run notrace because it is entered not completely "reconciled" */
|
||||
|
|
@ -392,7 +396,7 @@ notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs, unsigned
|
|||
ti_flags = READ_ONCE(current_thread_info()->flags);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && IS_ENABLED(CONFIG_PPC_FPU)) {
|
||||
if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && IS_ENABLED(CONFIG_PPC_FPU)) {
|
||||
if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) &&
|
||||
unlikely((ti_flags & _TIF_RESTORE_TM))) {
|
||||
restore_tm_state(regs);
|
||||
|
|
|
|||
Loading…
Reference in New Issue