mirror of https://gitee.com/openkylin/linux.git
ASoC: rsnd: setup BRGCKR/BRRA/BRRB when starting
Current rsnd driver setups BRGCKR/BRRA/BRRB when .probe timing. But it breaks sound after Suspend/Resume. These should be setups every start timing. This patch is tested on R-Car Gen3 Salvator-X board Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -34,6 +34,9 @@ struct rsnd_adg {
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struct clk_onecell_data onecell;
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struct rsnd_mod mod;
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u32 flags;
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u32 ckr;
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u32 rbga;
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u32 rbgb;
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int rbga_rate_for_441khz; /* RBGA */
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int rbgb_rate_for_48khz; /* RBGB */
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@ -316,9 +319,11 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
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struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct device *dev = rsnd_priv_to_dev(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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struct clk *clk;
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int i;
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u32 data;
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u32 ckr = 0;
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int sel_table[] = {
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[CLKA] = 0x1,
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[CLKB] = 0x2,
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@ -360,15 +365,14 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate)
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rsnd_adg_set_ssi_clk(ssi_mod, data);
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if (!(adg_mode_flags(adg) & LRCLK_ASYNC)) {
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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u32 ckr = 0;
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if (0 == (rate % 8000))
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ckr = 0x80000000;
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rsnd_mod_bset(adg_mod, BRGCKR, 0x80000000, ckr);
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}
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rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, adg->ckr | ckr);
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rsnd_mod_write(adg_mod, BRRA, adg->rbga);
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rsnd_mod_write(adg_mod, BRRB, adg->rbgb);
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dev_dbg(dev, "ADG: %s[%d] selects 0x%x for %d\n",
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rsnd_mod_name(ssi_mod), rsnd_mod_id(ssi_mod),
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data, rate);
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@ -421,7 +425,6 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
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struct rsnd_adg *adg)
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{
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struct clk *clk;
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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struct device *dev = rsnd_priv_to_dev(priv);
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struct device_node *np = dev->of_node;
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u32 ckr, rbgx, rbga, rbgb;
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@ -546,9 +549,9 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
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}
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}
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rsnd_mod_bset(adg_mod, BRGCKR, 0x80FF0000, ckr);
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rsnd_mod_write(adg_mod, BRRA, rbga);
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rsnd_mod_write(adg_mod, BRRB, rbgb);
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adg->ckr = ckr;
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adg->rbga = rbga;
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adg->rbgb = rbgb;
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for_each_rsnd_clkout(clk, adg, i)
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dev_dbg(dev, "clkout %d : %p : %ld\n", i, clk, clk_get_rate(clk));
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