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drm/i915: Allow p1 divider 2 on VLV 

According to VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm p1
can be 2-3 always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-09-24 21:26:26 +03:00 committed by Daniel Vetter
parent 811bbf0544
commit b99ab66301
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_display.c
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@ -330,7 +330,7 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
.m1 = { .min = 2, .max = 3 },
.m2 = { .min = 11, .max = 156 },
.p = { .min = 10, .max = 30 },
.p1 = { .min = 3, .max = 3 },
.p1 = { .min = 2, .max = 3 },
.p2 = { .dot_limit = 270000,
.p2_slow = 2, .p2_fast = 20 },
};