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dt-bindings: cpufreq: enhance MediaTek cpufreq dt-binding document
Update binding document with adding operating-points-v2 as the required property and the cooling level as the optional properties and adding more examples guiding people how to use MediaTek cpufreq driver for MediaTek SoCs. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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Sean Wang
Rafael J. Wysocki
parent
7e17ae8657
commit
bb33270c02
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@ -1,4 +1,5 @@
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Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
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Binding for MediaTek's CPUFreq driver
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=====================================
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Required properties:
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- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
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@ -9,6 +10,8 @@ Required properties:
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transition and not stable yet.
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Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
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generic clock consumer properties.
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- operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
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for detail.
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- proc-supply: Regulator for Vproc of CPU cluster.
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Optional properties:
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@ -17,9 +20,166 @@ Optional properties:
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Vsram to fit SoC specific needs. When absent, the voltage scaling
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flow is handled by hardware, hence no software "voltage tracking" is
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needed.
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- #cooling-cells:
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- cooling-min-level:
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- cooling-max-level:
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Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
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for detail.
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Example 1 (MT7623 SoC):
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cpu_opp_table: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-598000000 {
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opp-hz = /bits/ 64 <598000000>;
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opp-microvolt = <1050000>;
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};
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opp-747500000 {
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opp-hz = /bits/ 64 <747500000>;
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opp-microvolt = <1050000>;
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};
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opp-1040000000 {
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opp-hz = /bits/ 64 <1040000000>;
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opp-microvolt = <1150000>;
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};
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opp-1196000000 {
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opp-hz = /bits/ 64 <1196000000>;
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opp-microvolt = <1200000>;
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};
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opp-1300000000 {
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opp-hz = /bits/ 64 <1300000000>;
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opp-microvolt = <1300000>;
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&infracfg CLK_INFRA_CPUSEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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cooling-max-level = <7>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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Example 2 (MT8173 SoC):
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cpu_opp_table_a: opp_table_a {
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compatible = "operating-points-v2";
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opp-shared;
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opp-507000000 {
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opp-hz = /bits/ 64 <507000000>;
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opp-microvolt = <859000>;
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};
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opp-702000000 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <908000>;
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};
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opp-1001000000 {
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opp-hz = /bits/ 64 <1001000000>;
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opp-microvolt = <983000>;
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};
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opp-1105000000 {
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opp-hz = /bits/ 64 <1105000000>;
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opp-microvolt = <1009000>;
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};
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opp-1183000000 {
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opp-hz = /bits/ 64 <1183000000>;
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opp-microvolt = <1028000>;
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};
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opp-1404000000 {
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opp-hz = /bits/ 64 <1404000000>;
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opp-microvolt = <1083000>;
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};
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opp-1508000000 {
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opp-hz = /bits/ 64 <1508000000>;
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opp-microvolt = <1109000>;
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};
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opp-1573000000 {
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opp-hz = /bits/ 64 <1573000000>;
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opp-microvolt = <1125000>;
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};
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};
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cpu_opp_table_b: opp_table_b {
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compatible = "operating-points-v2";
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opp-shared;
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opp-507000000 {
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opp-hz = /bits/ 64 <507000000>;
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opp-microvolt = <828000>;
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};
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opp-702000000 {
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opp-hz = /bits/ 64 <702000000>;
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opp-microvolt = <867000>;
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};
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opp-1001000000 {
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opp-hz = /bits/ 64 <1001000000>;
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opp-microvolt = <927000>;
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};
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opp-1209000000 {
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opp-hz = /bits/ 64 <1209000000>;
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opp-microvolt = <968000>;
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};
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opp-1404000000 {
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opp-hz = /bits/ 64 <1007000000>;
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opp-microvolt = <1028000>;
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};
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opp-1612000000 {
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opp-hz = /bits/ 64 <1612000000>;
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opp-microvolt = <1049000>;
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};
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opp-1807000000 {
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opp-hz = /bits/ 64 <1807000000>;
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opp-microvolt = <1089000>;
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};
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opp-1989000000 {
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opp-hz = /bits/ 64 <1989000000>;
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opp-microvolt = <1125000>;
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};
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};
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Example:
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--------
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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@ -29,6 +189,7 @@ Example:
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table_a>;
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};
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cpu1: cpu@1 {
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@ -40,6 +201,7 @@ Example:
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clocks = <&infracfg CLK_INFRA_CA53SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table_a>;
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};
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cpu2: cpu@100 {
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@ -51,6 +213,7 @@ Example:
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table_b>;
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};
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cpu3: cpu@101 {
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@ -62,6 +225,7 @@ Example:
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clocks = <&infracfg CLK_INFRA_CA57SEL>,
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<&apmixedsys CLK_APMIXED_MAINPLL>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table_b>;
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};
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&cpu0 {
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