mirror of https://gitee.com/openkylin/linux.git
Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6
Conflicts: arch/arm/mach-mx3/mach-pcm037.c
This commit is contained in:
commit
bb3c9d4f85
|
@ -62,6 +62,15 @@ config MACH_MX31_3DS
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Include support for MX31PDK (3DS) platform. This includes specific
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configurations for the board and its peripherals.
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config MACH_MX31_3DS_MXC_NAND_USE_BBT
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bool "Make the MXC NAND driver use the in flash Bad Block Table"
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depends on MACH_MX31_3DS
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depends on MTD_NAND_MXC
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help
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Enable this if you want that the MXC NAND driver uses the in flash
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Bad Block Table to know what blocks are bad instead of scanning the
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entire flash looking for bad block markers.
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config MACH_MX31MOBOARD
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bool "Support mx31moboard platforms (EPFL Mobots group)"
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select ARCH_MX31
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|
@ -95,6 +104,7 @@ config MACH_PCM043
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config MACH_ARMADILLO5X0
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bool "Support Atmark Armadillo-500 Development Base Board"
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select ARCH_MX31
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select MXC_ULPI if USB_ULPI
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help
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Include support for Atmark Armadillo-500 platform. This includes
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specific configurations for the board and its peripherals.
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|
|
|
@ -468,6 +468,7 @@ static struct clk ahb_clk = {
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}
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DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
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DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
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@ -490,7 +491,7 @@ DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
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DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
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DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
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DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
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DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk);
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DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
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DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
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@ -514,7 +515,6 @@ DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk)
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DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
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DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
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DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
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DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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@ -572,7 +572,6 @@ static struct clk_lookup lookups[] = {
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_REGISTER_CLOCK(NULL, "iim", iim_clk)
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_REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
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_REGISTER_CLOCK(NULL, "mbx", mbx_clk)
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_REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
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};
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int __init mx31_clocks_init(unsigned long fref)
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|
|
|
@ -575,11 +575,26 @@ struct platform_device imx_ssi_device1 = {
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.resource = imx_ssi_resources1,
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};
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static int mx3_devices_init(void)
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static struct resource imx_wdt_resources[] = {
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{
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device imx_wdt_device0 = {
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.name = "imx-wdt",
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.id = 0,
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.num_resources = ARRAY_SIZE(imx_wdt_resources),
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.resource = imx_wdt_resources,
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};
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static int __init mx3_devices_init(void)
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{
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if (cpu_is_mx31()) {
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mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
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mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
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imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
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imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
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mxc_register_device(&mxc_rnga_device, NULL);
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}
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if (cpu_is_mx35()) {
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|
@ -597,6 +612,8 @@ static int mx3_devices_init(void)
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imx_ssi_resources0[1].end = MX35_INT_SSI1;
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imx_ssi_resources1[1].start = MX35_INT_SSI2;
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imx_ssi_resources1[1].end = MX35_INT_SSI2;
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imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
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imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
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}
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return 0;
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|
|
|
@ -25,4 +25,5 @@ extern struct platform_device mxc_spi_device1;
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extern struct platform_device mxc_spi_device2;
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extern struct platform_device imx_ssi_device0;
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extern struct platform_device imx_ssi_device1;
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extern struct platform_device imx_ssi_device1;
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extern struct platform_device imx_wdt_device0;
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|
|
|
@ -36,6 +36,9 @@
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#include <linux/input.h>
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#include <linux/gpio_keys.h>
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#include <linux/i2c.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/ulpi.h>
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#include <linux/delay.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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|
@ -52,6 +55,8 @@
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#include <mach/ipu.h>
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#include <mach/mx3fb.h>
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#include <mach/mxc_nand.h>
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#include <mach/mxc_ehci.h>
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#include <mach/ulpi.h>
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||||
|
||||
#include "devices.h"
|
||||
#include "crm_regs.h"
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|
@ -103,8 +108,158 @@ static int armadillo5x0_pins[] = {
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|||
/* I2C2 */
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MX31_PIN_CSPI2_MOSI__SCL,
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MX31_PIN_CSPI2_MISO__SDA,
|
||||
/* OTG */
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MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
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MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
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MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
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||||
MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
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MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
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MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
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MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
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MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
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MX31_PIN_USBOTG_CLK__USBOTG_CLK,
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MX31_PIN_USBOTG_DIR__USBOTG_DIR,
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MX31_PIN_USBOTG_NXT__USBOTG_NXT,
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MX31_PIN_USBOTG_STP__USBOTG_STP,
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||||
/* USB host 2 */
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IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
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||||
IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
|
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IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
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IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
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};
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/* USB */
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#if defined(CONFIG_USB_ULPI)
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#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
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#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
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||||
#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
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|
||||
#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
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PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
|
||||
|
||||
static int usbotg_init(struct platform_device *pdev)
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||||
{
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int err;
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||||
|
||||
mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
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mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
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|
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/* Chip already enabled by hardware */
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/* OTG phy reset*/
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err = gpio_request(OTG_RESET, "USB-OTG-RESET");
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if (err) {
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pr_err("Failed to request the usb otg reset gpio\n");
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||||
return err;
|
||||
}
|
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|
||||
err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
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if (err) {
|
||||
pr_err("Failed to reset the usb otg phy\n");
|
||||
goto otg_free_reset;
|
||||
}
|
||||
|
||||
gpio_set_value(OTG_RESET, 0/*LOW*/);
|
||||
mdelay(5);
|
||||
gpio_set_value(OTG_RESET, 1/*HIGH*/);
|
||||
|
||||
return 0;
|
||||
|
||||
otg_free_reset:
|
||||
gpio_free(OTG_RESET);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int usbh2_init(struct platform_device *pdev)
|
||||
{
|
||||
int err;
|
||||
|
||||
mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
|
||||
mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
|
||||
|
||||
mxc_iomux_set_gpr(MUX_PGP_UH2, true);
|
||||
|
||||
|
||||
/* Enable the chip */
|
||||
err = gpio_request(USBH2_CS, "USB-H2-CS");
|
||||
if (err) {
|
||||
pr_err("Failed to request the usb host 2 CS gpio\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
|
||||
if (err) {
|
||||
pr_err("Failed to drive the usb host 2 CS gpio\n");
|
||||
goto h2_free_cs;
|
||||
}
|
||||
|
||||
/* H2 phy reset*/
|
||||
err = gpio_request(USBH2_RESET, "USB-H2-RESET");
|
||||
if (err) {
|
||||
pr_err("Failed to request the usb host 2 reset gpio\n");
|
||||
goto h2_free_cs;
|
||||
}
|
||||
|
||||
err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
|
||||
if (err) {
|
||||
pr_err("Failed to reset the usb host 2 phy\n");
|
||||
goto h2_free_reset;
|
||||
}
|
||||
|
||||
gpio_set_value(USBH2_RESET, 0/*LOW*/);
|
||||
mdelay(5);
|
||||
gpio_set_value(USBH2_RESET, 1/*HIGH*/);
|
||||
|
||||
return 0;
|
||||
|
||||
h2_free_reset:
|
||||
gpio_free(USBH2_RESET);
|
||||
h2_free_cs:
|
||||
gpio_free(USBH2_CS);
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct mxc_usbh_platform_data usbotg_pdata = {
|
||||
.init = usbotg_init,
|
||||
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
|
||||
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
|
||||
};
|
||||
|
||||
static struct mxc_usbh_platform_data usbh2_pdata = {
|
||||
.init = usbh2_init,
|
||||
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
|
||||
.flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
|
||||
};
|
||||
#endif /* CONFIG_USB_ULPI */
|
||||
|
||||
/* RTC over I2C*/
|
||||
#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
|
||||
|
||||
|
@ -393,6 +548,17 @@ static void __init armadillo5x0_init(void)
|
|||
if (armadillo5x0_i2c_rtc.irq == 0)
|
||||
pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
|
||||
i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
|
||||
|
||||
/* USB */
|
||||
#if defined(CONFIG_USB_ULPI)
|
||||
usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
|
||||
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
|
||||
usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
|
||||
USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
|
||||
|
||||
mxc_register_device(&mxc_otg_host, &usbotg_pdata);
|
||||
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __init armadillo5x0_timer_init(void)
|
||||
|
|
|
@ -23,6 +23,9 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mfd/mc13783.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -31,26 +34,96 @@
|
|||
#include <asm/memory.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/board-mx31pdk.h>
|
||||
#include <mach/board-mx31_3ds.h>
|
||||
#include <mach/imx-uart.h>
|
||||
#include <mach/iomux-mx3.h>
|
||||
#include <mach/mxc_nand.h>
|
||||
#include <mach/spi.h>
|
||||
#include "devices.h"
|
||||
|
||||
/*!
|
||||
* @file mx31pdk.c
|
||||
* @file mx31_3ds.c
|
||||
*
|
||||
* @brief This file contains the board-specific initialization routines.
|
||||
*
|
||||
* @ingroup System
|
||||
*/
|
||||
|
||||
static int mx31pdk_pins[] = {
|
||||
static int mx31_3ds_pins[] = {
|
||||
/* UART1 */
|
||||
MX31_PIN_CTS1__CTS1,
|
||||
MX31_PIN_RTS1__RTS1,
|
||||
MX31_PIN_TXD1__TXD1,
|
||||
MX31_PIN_RXD1__RXD1,
|
||||
IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
|
||||
/* SPI 1 */
|
||||
MX31_PIN_CSPI2_SCLK__SCLK,
|
||||
MX31_PIN_CSPI2_MOSI__MOSI,
|
||||
MX31_PIN_CSPI2_MISO__MISO,
|
||||
MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
|
||||
MX31_PIN_CSPI2_SS0__SS0,
|
||||
MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
|
||||
/* MC13783 IRQ */
|
||||
IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
|
||||
};
|
||||
|
||||
/* Regulators */
|
||||
static struct regulator_init_data pwgtx_init = {
|
||||
.constraints = {
|
||||
.boot_on = 1,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
|
||||
{
|
||||
.id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
|
||||
.init_data = &pwgtx_init,
|
||||
}, {
|
||||
.id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
|
||||
.init_data = &pwgtx_init,
|
||||
},
|
||||
};
|
||||
|
||||
/* MC13783 */
|
||||
static struct mc13783_platform_data mc13783_pdata __initdata = {
|
||||
.regulators = mx31_3ds_regulators,
|
||||
.num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
|
||||
.flags = MC13783_USE_REGULATOR,
|
||||
};
|
||||
|
||||
/* SPI */
|
||||
static int spi1_internal_chipselect[] = {
|
||||
MXC_SPI_CS(0),
|
||||
MXC_SPI_CS(2),
|
||||
};
|
||||
|
||||
static struct spi_imx_master spi1_pdata = {
|
||||
.chipselect = spi1_internal_chipselect,
|
||||
.num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
|
||||
};
|
||||
|
||||
static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
|
||||
{
|
||||
.modalias = "mc13783",
|
||||
.max_speed_hz = 1000000,
|
||||
.bus_num = 1,
|
||||
.chip_select = 1, /* SS2 */
|
||||
.platform_data = &mc13783_pdata,
|
||||
.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
|
||||
.mode = SPI_CS_HIGH,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* NAND Flash
|
||||
*/
|
||||
static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
|
||||
.width = 1,
|
||||
.hw_ecc = 1,
|
||||
#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
|
||||
.flash_bbt = 1,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct imxuart_platform_data uart_pdata = {
|
||||
|
@ -95,7 +168,7 @@ static struct platform_device smsc911x_device = {
|
|||
* LEDs, switches, interrupts for Ethernet.
|
||||
*/
|
||||
|
||||
static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
|
||||
static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
|
||||
{
|
||||
uint32_t imr_val;
|
||||
uint32_t int_valid;
|
||||
|
@ -163,7 +236,7 @@ static struct irq_chip expio_irq_chip = {
|
|||
.unmask = expio_unmask_irq,
|
||||
};
|
||||
|
||||
static int __init mx31pdk_init_expio(void)
|
||||
static int __init mx31_3ds_init_expio(void)
|
||||
{
|
||||
int i;
|
||||
int ret;
|
||||
|
@ -176,7 +249,7 @@ static int __init mx31pdk_init_expio(void)
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n",
|
||||
pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
|
||||
__raw_readw(CPLD_CODE_VER_REG));
|
||||
|
||||
/*
|
||||
|
@ -201,7 +274,7 @@ static int __init mx31pdk_init_expio(void)
|
|||
set_irq_flags(i, IRQF_VALID);
|
||||
}
|
||||
set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
|
||||
set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler);
|
||||
set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -209,7 +282,7 @@ static int __init mx31pdk_init_expio(void)
|
|||
/*
|
||||
* This structure defines the MX31 memory map.
|
||||
*/
|
||||
static struct map_desc mx31pdk_io_desc[] __initdata = {
|
||||
static struct map_desc mx31_3ds_io_desc[] __initdata = {
|
||||
{
|
||||
.virtual = MX31_CS5_BASE_ADDR_VIRT,
|
||||
.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
|
||||
|
@ -221,10 +294,10 @@ static struct map_desc mx31pdk_io_desc[] __initdata = {
|
|||
/*
|
||||
* Set up static virtual mappings.
|
||||
*/
|
||||
static void __init mx31pdk_map_io(void)
|
||||
static void __init mx31_3ds_map_io(void)
|
||||
{
|
||||
mx31_map_io();
|
||||
iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc));
|
||||
iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
|
||||
}
|
||||
|
||||
/*!
|
||||
|
@ -232,35 +305,40 @@ static void __init mx31pdk_map_io(void)
|
|||
*/
|
||||
static void __init mxc_board_init(void)
|
||||
{
|
||||
mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins),
|
||||
"mx31pdk");
|
||||
mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
|
||||
"mx31_3ds");
|
||||
|
||||
mxc_register_device(&mxc_uart_device0, &uart_pdata);
|
||||
mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
|
||||
|
||||
if (!mx31pdk_init_expio())
|
||||
mxc_register_device(&mxc_spi_device1, &spi1_pdata);
|
||||
spi_register_board_info(mx31_3ds_spi_devs,
|
||||
ARRAY_SIZE(mx31_3ds_spi_devs));
|
||||
|
||||
if (!mx31_3ds_init_expio())
|
||||
platform_device_register(&smsc911x_device);
|
||||
}
|
||||
|
||||
static void __init mx31pdk_timer_init(void)
|
||||
static void __init mx31_3ds_timer_init(void)
|
||||
{
|
||||
mx31_clocks_init(26000000);
|
||||
}
|
||||
|
||||
static struct sys_timer mx31pdk_timer = {
|
||||
.init = mx31pdk_timer_init,
|
||||
static struct sys_timer mx31_3ds_timer = {
|
||||
.init = mx31_3ds_timer_init,
|
||||
};
|
||||
|
||||
/*
|
||||
* The following uses standard kernel macros defined in arch.h in order to
|
||||
* initialize __mach_desc_MX31PDK data structure.
|
||||
* initialize __mach_desc_MX31_3DS data structure.
|
||||
*/
|
||||
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
|
||||
/* Maintainer: Freescale Semiconductor, Inc. */
|
||||
.phys_io = MX31_AIPS1_BASE_ADDR,
|
||||
.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
|
||||
.boot_params = MX3x_PHYS_OFFSET + 0x100,
|
||||
.map_io = mx31pdk_map_io,
|
||||
.map_io = mx31_3ds_map_io,
|
||||
.init_irq = mx31_init_irq,
|
||||
.init_machine = mxc_board_init,
|
||||
.timer = &mx31pdk_timer,
|
||||
.timer = &mx31_3ds_timer,
|
||||
MACHINE_END
|
||||
|
|
|
@ -35,7 +35,6 @@
|
|||
#include <linux/can/platform/sja1000.h>
|
||||
#include <linux/usb/otg.h>
|
||||
#include <linux/usb/ulpi.h>
|
||||
#include <linux/fsl_devices.h>
|
||||
#include <linux/gfp.h>
|
||||
|
||||
#include <media/soc_camera.h>
|
||||
|
|
|
@ -28,7 +28,6 @@
|
|||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
|
@ -206,5 +205,6 @@ void __init mx31lite_db_init(void)
|
|||
mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
|
||||
mxc_register_device(&mxc_spi_device0, &spi0_pdata);
|
||||
platform_device_register(&litekit_led_device);
|
||||
mxc_register_device(&imx_wdt_device0, NULL);
|
||||
}
|
||||
|
||||
|
|
|
@ -757,7 +757,7 @@ DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
|
|||
|
||||
/* GPT */
|
||||
DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
|
||||
NULL, NULL, &ipg_perclk, NULL);
|
||||
NULL, NULL, &ipg_clk, NULL);
|
||||
DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
|
||||
NULL, NULL, &ipg_clk, NULL);
|
||||
|
||||
|
|
|
@ -14,9 +14,62 @@
|
|||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static int cpu_silicon_rev = -1;
|
||||
|
||||
#define SI_REV 0x48
|
||||
|
||||
static void query_silicon_parameter(void)
|
||||
{
|
||||
void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
|
||||
u32 rev;
|
||||
|
||||
if (!rom) {
|
||||
cpu_silicon_rev = -EINVAL;
|
||||
return;
|
||||
}
|
||||
|
||||
rev = readl(rom + SI_REV);
|
||||
switch (rev) {
|
||||
case 0x1:
|
||||
cpu_silicon_rev = MX51_CHIP_REV_1_0;
|
||||
break;
|
||||
case 0x2:
|
||||
cpu_silicon_rev = MX51_CHIP_REV_1_1;
|
||||
break;
|
||||
case 0x10:
|
||||
cpu_silicon_rev = MX51_CHIP_REV_2_0;
|
||||
break;
|
||||
case 0x20:
|
||||
cpu_silicon_rev = MX51_CHIP_REV_3_0;
|
||||
break;
|
||||
default:
|
||||
cpu_silicon_rev = 0;
|
||||
}
|
||||
|
||||
iounmap(rom);
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns:
|
||||
* the silicon revision of the cpu
|
||||
* -EINVAL - not a mx51
|
||||
*/
|
||||
int mx51_revision(void)
|
||||
{
|
||||
if (!cpu_is_mx51())
|
||||
return -EINVAL;
|
||||
|
||||
if (cpu_silicon_rev == -1)
|
||||
query_silicon_parameter();
|
||||
|
||||
return cpu_silicon_rev;
|
||||
}
|
||||
EXPORT_SYMBOL(mx51_revision);
|
||||
|
||||
static int __init post_cpu_init(void)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
|
|
@ -34,11 +34,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
|
||||
.length = MX51_DEBUG_SIZE,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = MX51_TZIC_BASE_ADDR_VIRT,
|
||||
.pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
|
||||
.length = MX51_TZIC_SIZE,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = MX51_AIPS1_BASE_ADDR_VIRT,
|
||||
.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
|
||||
|
@ -54,11 +49,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
|
|||
.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
|
||||
.length = MX51_AIPS2_SIZE,
|
||||
.type = MT_DEVICE
|
||||
}, {
|
||||
.virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,
|
||||
.pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),
|
||||
.length = MX51_NFC_AXI_SIZE,
|
||||
.type = MT_DEVICE
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -69,14 +59,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
|
|||
*/
|
||||
void __init mx51_map_io(void)
|
||||
{
|
||||
u32 tzic_addr;
|
||||
|
||||
if (mx51_revision() < MX51_CHIP_REV_2_0)
|
||||
tzic_addr = 0x8FFFC000;
|
||||
else
|
||||
tzic_addr = 0xE0003000;
|
||||
mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr);
|
||||
|
||||
mxc_set_cpu_type(MXC_CPU_MX51);
|
||||
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
|
||||
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
|
||||
|
@ -85,5 +67,17 @@ void __init mx51_map_io(void)
|
|||
|
||||
void __init mx51_init_irq(void)
|
||||
{
|
||||
tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
|
||||
unsigned long tzic_addr;
|
||||
void __iomem *tzic_virt;
|
||||
|
||||
if (mx51_revision() < MX51_CHIP_REV_2_0)
|
||||
tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
|
||||
else
|
||||
tzic_addr = MX51_TZIC_BASE_ADDR;
|
||||
|
||||
tzic_virt = ioremap(tzic_addr, SZ_16K);
|
||||
if (!tzic_virt)
|
||||
panic("unable to map TZIC interrupt controller\n");
|
||||
|
||||
tzic_init_irq(tzic_virt);
|
||||
}
|
||||
|
|
|
@ -8,8 +8,8 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
|
||||
#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
|
||||
#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
|
||||
#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
|
||||
|
||||
/* Definitions for components on the Debug board */
|
||||
|
||||
|
@ -56,4 +56,4 @@
|
|||
|
||||
#define MXC_MAX_EXP_IO_LINES 16
|
||||
|
||||
#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */
|
||||
#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
|
|
@ -14,7 +14,7 @@
|
|||
* FB100000 70000000 1M SPBA 0
|
||||
* FB000000 73F00000 1M AIPS 1
|
||||
* FB200000 83F00000 1M AIPS 2
|
||||
* FA100000 8FFFC000 16K TZIC (interrupt controller)
|
||||
* 8FFFC000 16K TZIC (interrupt controller)
|
||||
* 90000000 256M CSD0 SDRAM/DDR
|
||||
* A0000000 256M CSD1 SDRAM/DDR
|
||||
* B0000000 128M CS0 Flash
|
||||
|
@ -23,10 +23,16 @@
|
|||
* C8000000 64M CS3 Flash
|
||||
* CC000000 32M CS4 SRAM
|
||||
* CE000000 32M CS5 SRAM
|
||||
* F9000000 CFFF0000 64K NFC (NAND Flash AXI)
|
||||
* CFFF0000 64K NFC (NAND Flash AXI)
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* IROM
|
||||
*/
|
||||
#define MX51_IROM_BASE_ADDR 0x0
|
||||
#define MX51_IROM_SIZE SZ_64K
|
||||
|
||||
/*
|
||||
* IRAM
|
||||
*/
|
||||
|
@ -40,7 +46,6 @@
|
|||
* NFC
|
||||
*/
|
||||
#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
|
||||
#define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000
|
||||
#define MX51_NFC_AXI_SIZE SZ_64K
|
||||
|
||||
/*
|
||||
|
@ -49,9 +54,8 @@
|
|||
#define MX51_GPU_BASE_ADDR 0x20000000
|
||||
#define MX51_GPU2D_BASE_ADDR 0xD0000000
|
||||
|
||||
#define MX51_TZIC_BASE_ADDR 0x8FFFC000
|
||||
#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000
|
||||
#define MX51_TZIC_SIZE SZ_16K
|
||||
#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000
|
||||
#define MX51_TZIC_BASE_ADDR 0xE0000000
|
||||
|
||||
#define MX51_DEBUG_BASE_ADDR 0x60000000
|
||||
#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000
|
||||
|
@ -232,12 +236,10 @@
|
|||
#define MX51_IO_ADDRESS(x) \
|
||||
(void __iomem *) \
|
||||
(MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
|
||||
MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \
|
||||
MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
|
||||
MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
|
||||
MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
|
||||
MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
|
||||
MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
|
||||
MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
|
||||
0xDEADBEEF)
|
||||
|
||||
/*
|
||||
|
@ -246,9 +248,6 @@
|
|||
#define MX51_IRAM_IO_ADDRESS(x) \
|
||||
(((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
|
||||
|
||||
#define MX51_TZIC_IO_ADDRESS(x) \
|
||||
(((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
|
||||
|
||||
#define MX51_DEBUG_IO_ADDRESS(x) \
|
||||
(((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
|
||||
|
||||
|
@ -261,9 +260,6 @@
|
|||
#define MX51_AIPS2_IO_ADDRESS(x) \
|
||||
(((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
|
||||
|
||||
#define MX51_NFC_AXI_IO_ADDRESS(x) \
|
||||
(((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
|
||||
|
||||
#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
|
||||
|
||||
/*
|
||||
|
@ -443,12 +439,7 @@
|
|||
|
||||
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
|
||||
|
||||
extern unsigned int system_rev;
|
||||
|
||||
static inline unsigned int mx51_revision(void)
|
||||
{
|
||||
return system_rev;
|
||||
}
|
||||
extern int mx51_revision(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_MXC_MX51_H__ */
|
||||
|
|
|
@ -66,6 +66,7 @@ static inline void flush(void)
|
|||
#define MX2X_UART1_BASE_ADDR 0x1000a000
|
||||
#define MX3X_UART1_BASE_ADDR 0x43F90000
|
||||
#define MX3X_UART2_BASE_ADDR 0x43F94000
|
||||
#define MX51_UART1_BASE_ADDR 0x73fbc000
|
||||
|
||||
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
|
||||
{
|
||||
|
@ -101,6 +102,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
|
|||
case MACH_TYPE_MAGX_ZN5:
|
||||
uart_base = MX3X_UART2_BASE_ADDR;
|
||||
break;
|
||||
case MACH_TYPE_MX51_BABBAGE:
|
||||
uart_base = MX51_UART1_BASE_ADDR;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue