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clk: at91: optimize clk_round_rate() for AUDIO_PLL 

Stop the search for parent rate when exact match is found.

This makes for 3 clk_round_rate() calls instead of 64 of them on
SAMA5D2-based board when searching for 12.288MHz clock.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Michał Mirosław 2018-12-18 12:20:48 +01:00 committed by Stephen Boyd
parent 77977b8004
commit bb631af3d5
1 changed files with 8 additions and 1 deletions
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9
drivers/clk/at91/clk-audio-pll.c
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@ -340,7 +340,12 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
rate, *parent_rate);
for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) {
if (!rate)
return 0;
best_parent_rate = clk_round_rate(pclk->clk, 1);
div = max(best_parent_rate / rate, 1UL);
for (; div <= AUDIO_PLL_QDPMC_MAX; div++) {
best_parent_rate = clk_round_rate(pclk->clk, rate * div);
tmp_rate = best_parent_rate / div;
tmp_diff = abs(rate - tmp_rate);
@ -350,6 +355,8 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
best_rate = tmp_rate;
best_diff = tmp_diff;
tmp_qd = div;
if (!best_diff)
break; /* got exact match */
}
}