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mmc: sdhci-esdhc-imx: add CMDQ support
Add CMDQ support for imx8qm/imx8qxp. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> [Ulf: Rebased on top of latest changes] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
BOUGH CHEN
Ulf Hansson
parent
401059df9b
commit
bb6e358169
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@ -224,6 +224,7 @@ config MMC_SDHCI_ESDHC_IMX
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depends on ARCH_MXC
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depends on MMC_SDHCI_PLTFM
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select MMC_SDHCI_IO_ACCESSORS
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select MMC_CQHCI
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help
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This selects the Freescale eSDHC/uSDHC controller support
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found on i.MX25, i.MX35 i.MX5x and i.MX6x.
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@ -25,6 +25,7 @@
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#include <linux/pm_runtime.h>
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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#include "cqhci.h"
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#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
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#define ESDHC_CTRL_D3CD 0x08
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@ -104,6 +105,9 @@
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*/
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#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
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/* the address offset of CQHCI */
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#define ESDHC_CQHCI_ADDR_OFFSET 0x100
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/*
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* The CMDTYPE of the CMD register (offset 0xE) should be set to
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* "11" when the STOP CMD12 is issued on imx53 to abort one
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@ -147,6 +151,8 @@
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#define ESDHC_FLAG_ERR010450 BIT(10)
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/* The IP supports HS400ES mode */
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#define ESDHC_FLAG_HS400_ES BIT(11)
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/* The IP has Host Controller Interface for Command Queuing */
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#define ESDHC_FLAG_CQHCI BIT(12)
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struct esdhc_soc_data {
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u32 flags;
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@ -198,7 +204,8 @@ static const struct esdhc_soc_data usdhc_imx7d_data = {
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static struct esdhc_soc_data usdhc_imx8qxp_data = {
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.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
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| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
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| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
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| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
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| ESDHC_FLAG_CQHCI,
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};
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struct pltfm_imx_data {
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@ -1094,6 +1101,19 @@ static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
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SDHCI_TIMEOUT_CONTROL);
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}
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static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
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{
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int cmd_error = 0;
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int data_error = 0;
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if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
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return intmask;
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cqhci_irq(host->mmc, intmask, cmd_error, data_error);
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return 0;
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}
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static struct sdhci_ops sdhci_esdhc_ops = {
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.read_l = esdhc_readl_le,
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.read_w = esdhc_readw_le,
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@ -1110,6 +1130,7 @@ static struct sdhci_ops sdhci_esdhc_ops = {
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.set_bus_width = esdhc_pltfm_set_bus_width,
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.set_uhs_signaling = esdhc_set_uhs_signaling,
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.reset = esdhc_reset,
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.irq = esdhc_cqhci_irq,
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};
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static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
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@ -1185,6 +1206,55 @@ static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
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}
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}
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static void esdhc_cqe_enable(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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u32 reg;
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u16 mode;
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int count = 10;
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/*
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* CQE gets stuck if it sees Buffer Read Enable bit set, which can be
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* the case after tuning, so ensure the buffer is drained.
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*/
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reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
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while (reg & SDHCI_DATA_AVAILABLE) {
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sdhci_readl(host, SDHCI_BUFFER);
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reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
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if (count-- == 0) {
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dev_warn(mmc_dev(host->mmc),
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"CQE may get stuck because the Buffer Read Enable bit is set\n");
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break;
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}
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mdelay(1);
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}
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/*
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* Runtime resume will reset the entire host controller, which
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* will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL.
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* Here set DMAEN and BCEN when enable CMDQ.
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*/
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mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
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if (host->flags & SDHCI_REQ_USE_DMA)
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mode |= SDHCI_TRNS_DMA;
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if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
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mode |= SDHCI_TRNS_BLK_CNT_EN;
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sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
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sdhci_cqe_enable(mmc);
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}
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static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
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{
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sdhci_dumpregs(mmc_priv(mmc));
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}
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static const struct cqhci_host_ops esdhc_cqhci_ops = {
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.enable = esdhc_cqe_enable,
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.disable = sdhci_cqe_disable,
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.dumpregs = esdhc_sdhci_dumpregs,
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};
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#ifdef CONFIG_OF
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static int
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sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
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@ -1316,6 +1386,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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of_match_device(imx_esdhc_dt_ids, &pdev->dev);
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_host *host;
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struct cqhci_host *cq_host;
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int err;
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struct pltfm_imx_data *imx_data;
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@ -1406,6 +1477,22 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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esdhc_hs400_enhanced_strobe;
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}
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if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
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host->mmc->caps2 |= MMC_CAP2_CQE;
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cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
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if (IS_ERR(cq_host)) {
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err = PTR_ERR(cq_host);
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goto disable_ahb_clk;
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}
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cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
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cq_host->ops = &esdhc_cqhci_ops;
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err = cqhci_init(cq_host, host->mmc, false);
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if (err)
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goto disable_ahb_clk;
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}
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if (of_id)
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err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
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else
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@ -1466,6 +1553,13 @@ static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
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static int sdhci_esdhc_suspend(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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int ret;
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if (host->mmc->caps2 & MMC_CAP2_CQE) {
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ret = cqhci_suspend(host->mmc);
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if (ret)
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return ret;
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}
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if (host->tuning_mode != SDHCI_TUNING_MODE_3)
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mmc_retune_needed(host->mmc);
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@ -1476,11 +1570,19 @@ static int sdhci_esdhc_suspend(struct device *dev)
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static int sdhci_esdhc_resume(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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int ret;
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/* re-initialize hw state in case it's lost in low power mode */
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sdhci_esdhc_imx_hwinit(host);
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return sdhci_resume_host(host);
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ret = sdhci_resume_host(host);
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if (ret)
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return ret;
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if (host->mmc->caps2 & MMC_CAP2_CQE)
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ret = cqhci_resume(host->mmc);
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return ret;
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}
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#endif
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@ -1492,6 +1594,12 @@ static int sdhci_esdhc_runtime_suspend(struct device *dev)
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struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
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int ret;
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if (host->mmc->caps2 & MMC_CAP2_CQE) {
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ret = cqhci_suspend(host->mmc);
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if (ret)
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return ret;
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}
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ret = sdhci_runtime_suspend_host(host);
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if (ret)
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return ret;
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@ -1535,7 +1643,10 @@ static int sdhci_esdhc_runtime_resume(struct device *dev)
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if (err)
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goto disable_ipg_clk;
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return 0;
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if (host->mmc->caps2 & MMC_CAP2_CQE)
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err = cqhci_resume(host->mmc);
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return err;
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disable_ipg_clk:
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if (!sdhci_sdio_irq_enabled(host))
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