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drm/ingenic: Add support for 30-bit modes 

Starting from the JZ4760 SoC, the primary and overlay planes support
30-bit pixel modes (10 bits per color component). Add support for these
in the ingenic-drm driver.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200926170501.1109197-7-paul@crapouillou.net
This commit is contained in:
Paul Cercueil 2020-09-26 19:05:00 +02:00
parent 3d705fb0dc
commit bb85760572
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GPG Key ID: 73EE6BD2274ABD41
2 changed files with 9 additions and 0 deletions
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8
drivers/gpu/drm/ingenic/ingenic-drm-drv.c
View File

@ -458,6 +458,9 @@ void ingenic_drm_plane_config(struct device *dev,
case DRM_FORMAT_XRGB8888: case DRM_FORMAT_XRGB8888:
ctrl |= JZ_LCD_OSDCTRL_BPP_18_24; ctrl |= JZ_LCD_OSDCTRL_BPP_18_24;
break; break;
case DRM_FORMAT_XRGB2101010:
ctrl |= JZ_LCD_OSDCTRL_BPP_30;
break;
} }
regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL, regmap_update_bits(priv->map, JZ_REG_LCD_OSDCTRL,
@ -473,6 +476,9 @@ void ingenic_drm_plane_config(struct device *dev,
case DRM_FORMAT_XRGB8888: case DRM_FORMAT_XRGB8888:
ctrl |= JZ_LCD_CTRL_BPP_18_24; ctrl |= JZ_LCD_CTRL_BPP_18_24;
break; break;
case DRM_FORMAT_XRGB2101010:
ctrl |= JZ_LCD_CTRL_BPP_30;
break;
} }
regmap_update_bits(priv->map, JZ_REG_LCD_CTRL, regmap_update_bits(priv->map, JZ_REG_LCD_CTRL,
@ -1222,12 +1228,14 @@ static const u32 jz4770_formats_f1[] = {
DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGB565, DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888, DRM_FORMAT_XRGB8888,
DRM_FORMAT_XRGB2101010,
}; };
static const u32 jz4770_formats_f0[] = { static const u32 jz4770_formats_f0[] = {
DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGB565, DRM_FORMAT_RGB565,
DRM_FORMAT_XRGB8888, DRM_FORMAT_XRGB8888,
DRM_FORMAT_XRGB2101010,
}; };
static const struct jz_soc_info jz4740_soc_info = { static const struct jz_soc_info jz4740_soc_info = {

1
drivers/gpu/drm/ingenic/ingenic-drm.h
View File

@ -124,6 +124,7 @@
#define JZ_LCD_CTRL_BPP_8 0x3 #define JZ_LCD_CTRL_BPP_8 0x3
#define JZ_LCD_CTRL_BPP_15_16 0x4 #define JZ_LCD_CTRL_BPP_15_16 0x4
#define JZ_LCD_CTRL_BPP_18_24 0x5 #define JZ_LCD_CTRL_BPP_18_24 0x5
#define JZ_LCD_CTRL_BPP_30 0x7
#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) #define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7)
#define JZ_LCD_CMD_SOF_IRQ BIT(31) #define JZ_LCD_CMD_SOF_IRQ BIT(31)