mirror of https://gitee.com/openkylin/linux.git
[ARM] armv7: add support for ARMv7 cores.
This patch adds support for the ARMv7 cores. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas
Russell King
parent
5b94f675f5
commit
bbe888864e
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@ -0,0 +1,32 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* Function: v7_early_abort
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*
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* Params : r2 = address of aborted instruction
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* : r3 = saved SPSR
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*
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r2-r8 = corrupted
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* : r9 = preserved
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* : sp = pointer to registers
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*
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* Purpose : obtain information about current aborted instruction.
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*/
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.align 5
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ENTRY(v7_early_abort)
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/*
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* The effect of data aborts on on the exclusive access monitor are
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* UNPREDICTABLE. Do a CLREX to clear the state
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*/
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clrex
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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/*
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* V6 code adjusts the returned DFSR.
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* New designs should not need to patch up faults.
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*/
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mov pc, lr
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@ -0,0 +1,253 @@
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/*
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* linux/arch/arm/mm/cache-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2005 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7 processor support.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include "proc-macros.S"
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/*
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* v7_flush_dcache_all()
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*
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* Flush the whole D-cache.
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*
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* Corrupted registers: r0-r5, r7, r9-r11
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v7_flush_dcache_all)
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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loop1:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop2:
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mov r9, r4 @ create working copy of max way size
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loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3
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subs r7, r7, #1 @ decrement the index
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bge loop2
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt loop1
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb
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mov pc, lr
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/*
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* v7_flush_cache_all()
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*
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* Flush the entire cache system.
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* The data cache flush is now achieved using atomic clean / invalidates
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* working outwards from L1 cache. This is done using Set/Way based cache
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* maintainance instructions.
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* The instruction cache can still be invalidated back to the point of
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* unification in a single instruction.
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*
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*/
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ENTRY(v7_flush_kern_cache_all)
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stmfd sp!, {r4-r5, r7, r9-r11, lr}
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bl v7_flush_dcache_all
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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ldmfd sp!, {r4-r5, r7, r9-r11, lr}
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mov pc, lr
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/*
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* v7_flush_cache_all()
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*
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* Flush all TLB entries in a particular address space
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v7_flush_user_cache_all)
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/*FALLTHROUGH*/
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/*
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* v7_flush_cache_range(start, end, flags)
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*
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* Flush a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - flags - vm_area_struct flags describing address space
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*
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* It is assumed that:
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* - we have a VIPT cache.
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*/
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ENTRY(v7_flush_user_cache_range)
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mov pc, lr
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/*
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* v7_coherent_kern_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*
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* It is assumed that:
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* - the Icache does not read data from the write buffer
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*/
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ENTRY(v7_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* v7_coherent_user_range(start,end)
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*
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* Ensure that the I and D caches are coherent within specified
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* region. This is typically used when code has been written to
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* a memory region, and will be executed.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*
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* It is assumed that:
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* - the Icache does not read data from the write buffer
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*/
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ENTRY(v7_coherent_user_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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1: mcr p15, 0, r0, c7, c11, 1 @ clean D line to the point of unification
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dsb
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
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dsb
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isb
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mov pc, lr
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/*
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* v7_flush_kern_dcache_page(kaddr)
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*
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* Ensure that the data held in the page kaddr is written back
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* to the page in question.
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*
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* - kaddr - kernel address (guaranteed to be page aligned)
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*/
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ENTRY(v7_flush_kern_dcache_page)
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dcache_line_size r2, r3
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add r1, r0, #PAGE_SZ
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb
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mov pc, lr
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/*
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* v7_dma_inv_range(start,end)
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*
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* Invalidate the data cache within the specified region; we will
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* be performing a DMA operation in this region and we want to
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* purge old data in the cache.
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*
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(v7_dma_inv_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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tst r0, r3
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bic r0, r0, r3
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mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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tst r1, r3
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bic r1, r1, r3
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mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
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1:
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb
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mov pc, lr
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/*
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* v7_dma_clean_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(v7_dma_clean_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb
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mov pc, lr
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/*
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* v7_dma_flush_range(start,end)
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* - start - virtual start address of region
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* - end - virtual end address of region
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*/
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ENTRY(v7_dma_flush_range)
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dcache_line_size r2, r3
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sub r3, r2, #1
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bic r0, r0, r3
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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add r0, r0, r2
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cmp r0, r1
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blo 1b
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dsb
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mov pc, lr
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__INITDATA
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.type v7_cache_fns, #object
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ENTRY(v7_cache_fns)
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.long v7_flush_kern_cache_all
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.long v7_flush_user_cache_all
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.long v7_flush_user_cache_range
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.long v7_coherent_kern_range
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.long v7_coherent_user_range
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.long v7_flush_kern_dcache_page
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.long v7_dma_inv_range
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.long v7_dma_clean_range
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.long v7_dma_flush_range
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.size v7_cache_fns, . - v7_cache_fns
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@ -59,3 +59,15 @@
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.word \ucset
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.word \ucset
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#endif
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#endif
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.endm
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.endm
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/*
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* cache_line_size - get the cache line size from the CSIDR register
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* (available on ARMv7+). It assumes that the CSSR register was configured
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* to access the L1 data cache CSIDR.
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*/
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.macro dcache_line_size, reg, tmp
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mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR
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and \tmp, \tmp, #7 @ cache line size encoding
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mov \reg, #16 @ size offset
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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@ -0,0 +1,262 @@
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/*
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* linux/arch/arm/mm/proc-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7 processor support.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/elf.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#define TTB_C (1 << 0)
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#define TTB_S (1 << 1)
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#define TTB_RGN_OC_WT (2 << 3)
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#define TTB_RGN_OC_WB (3 << 3)
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ENTRY(cpu_v7_proc_init)
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mov pc, lr
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ENTRY(cpu_v7_proc_fin)
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mov pc, lr
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/*
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* cpu_v7_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*
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* It is assumed that:
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*/
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.align 5
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ENTRY(cpu_v7_reset)
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mov pc, r0
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/*
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* cpu_v7_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v7_do_idle)
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.long 0xe320f003 @ ARM V7 WFI instruction
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mov pc, lr
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ENTRY(cpu_v7_dcache_clean_area)
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#ifndef TLB_CAN_READ_FROM_L1_CACHE
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dcache_line_size r2, r3
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, r2
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subs r1, r1, r2
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bhi 1b
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dsb
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#endif
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mov pc, lr
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys
|
||||||
|
*
|
||||||
|
* - pgd_phys - physical address of new TTB
|
||||||
|
*
|
||||||
|
* It is assumed that:
|
||||||
|
* - we are not using split page tables
|
||||||
|
*/
|
||||||
|
ENTRY(cpu_v7_switch_mm)
|
||||||
|
mov r2, #0
|
||||||
|
ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
|
||||||
|
orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
|
||||||
|
mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
|
||||||
|
isb
|
||||||
|
1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
|
||||||
|
isb
|
||||||
|
mcr p15, 0, r1, c13, c0, 1 @ set context ID
|
||||||
|
isb
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* cpu_v7_set_pte_ext(ptep, pte)
|
||||||
|
*
|
||||||
|
* Set a level 2 translation table entry.
|
||||||
|
*
|
||||||
|
* - ptep - pointer to level 2 translation table entry
|
||||||
|
* (hardware version is stored at -1024 bytes)
|
||||||
|
* - pte - PTE value to store
|
||||||
|
* - ext - value for extended PTE bits
|
||||||
|
*
|
||||||
|
* Permissions:
|
||||||
|
* YUWD APX AP1 AP0 SVC User
|
||||||
|
* 0xxx 0 0 0 no acc no acc
|
||||||
|
* 100x 1 0 1 r/o no acc
|
||||||
|
* 10x0 1 0 1 r/o no acc
|
||||||
|
* 1011 0 0 1 r/w no acc
|
||||||
|
* 110x 0 1 0 r/w r/o
|
||||||
|
* 11x0 0 1 0 r/w r/o
|
||||||
|
* 1111 0 1 1 r/w r/w
|
||||||
|
*/
|
||||||
|
ENTRY(cpu_v7_set_pte_ext)
|
||||||
|
str r1, [r0], #-2048 @ linux version
|
||||||
|
|
||||||
|
bic r3, r1, #0x000003f0
|
||||||
|
bic r3, r3, #0x00000003
|
||||||
|
orr r3, r3, r2
|
||||||
|
orr r3, r3, #PTE_EXT_AP0 | 2
|
||||||
|
|
||||||
|
tst r1, #L_PTE_WRITE
|
||||||
|
tstne r1, #L_PTE_DIRTY
|
||||||
|
orreq r3, r3, #PTE_EXT_APX
|
||||||
|
|
||||||
|
tst r1, #L_PTE_USER
|
||||||
|
orrne r3, r3, #PTE_EXT_AP1
|
||||||
|
tstne r3, #PTE_EXT_APX
|
||||||
|
bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
|
||||||
|
|
||||||
|
tst r1, #L_PTE_YOUNG
|
||||||
|
biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK
|
||||||
|
|
||||||
|
tst r1, #L_PTE_EXEC
|
||||||
|
orreq r3, r3, #PTE_EXT_XN
|
||||||
|
|
||||||
|
tst r1, #L_PTE_PRESENT
|
||||||
|
moveq r3, #0
|
||||||
|
|
||||||
|
str r3, [r0]
|
||||||
|
mcr p15, 0, r0, c7, c10, 1 @ flush_pte
|
||||||
|
mov pc, lr
|
||||||
|
|
||||||
|
cpu_v7_name:
|
||||||
|
.ascii "ARMv7 Processor"
|
||||||
|
.align
|
||||||
|
|
||||||
|
.section ".text.init", #alloc, #execinstr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* __v7_setup
|
||||||
|
*
|
||||||
|
* Initialise TLB, Caches, and MMU state ready to switch the MMU
|
||||||
|
* on. Return in r0 the new CP15 C1 control register setting.
|
||||||
|
*
|
||||||
|
* We automatically detect if we have a Harvard cache, and use the
|
||||||
|
* Harvard cache control instructions insead of the unified cache
|
||||||
|
* control instructions.
|
||||||
|
*
|
||||||
|
* This should be able to cover all ARMv7 cores.
|
||||||
|
*
|
||||||
|
* It is assumed that:
|
||||||
|
* - cache type register is implemented
|
||||||
|
*/
|
||||||
|
__v7_setup:
|
||||||
|
adr r12, __v7_setup_stack @ the local stack
|
||||||
|
stmia r12, {r0-r5, r7, r9, r11, lr}
|
||||||
|
bl v7_flush_dcache_all
|
||||||
|
ldmia r12, {r0-r5, r7, r9, r11, lr}
|
||||||
|
mov r10, #0
|
||||||
|
#ifdef HARVARD_CACHE
|
||||||
|
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
|
||||||
|
#endif
|
||||||
|
dsb
|
||||||
|
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
|
||||||
|
mcr p15, 0, r10, c2, c0, 2 @ TTB control register
|
||||||
|
orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB
|
||||||
|
mcr p15, 0, r4, c2, c0, 0 @ load TTB0
|
||||||
|
mcr p15, 0, r4, c2, c0, 1 @ load TTB1
|
||||||
|
mov r10, #0x1f @ domains 0, 1 = manager
|
||||||
|
mcr p15, 0, r10, c3, c0, 0 @ load domain access register
|
||||||
|
#ifndef CONFIG_CPU_L2CACHE_DISABLE
|
||||||
|
@ L2 cache configuration in the L2 aux control register
|
||||||
|
mrc p15, 1, r10, c9, c0, 2
|
||||||
|
bic r10, r10, #(1 << 16) @ L2 outer cache
|
||||||
|
mcr p15, 1, r10, c9, c0, 2
|
||||||
|
@ L2 cache is enabled in the aux control register
|
||||||
|
mrc p15, 0, r10, c1, c0, 1
|
||||||
|
orr r10, r10, #2
|
||||||
|
mcr p15, 0, r10, c1, c0, 1
|
||||||
|
#endif
|
||||||
|
mrc p15, 0, r0, c1, c0, 0 @ read control register
|
||||||
|
ldr r10, cr1_clear @ get mask for bits to clear
|
||||||
|
bic r0, r0, r10 @ clear bits them
|
||||||
|
ldr r10, cr1_set @ get mask for bits to set
|
||||||
|
orr r0, r0, r10 @ set them
|
||||||
|
mov pc, lr @ return to head.S:__ret
|
||||||
|
|
||||||
|
/*
|
||||||
|
* V X F I D LR
|
||||||
|
* .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
|
||||||
|
* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
|
||||||
|
* 0 110 0011 1.00 .111 1101 < we want
|
||||||
|
*/
|
||||||
|
.type cr1_clear, #object
|
||||||
|
.type cr1_set, #object
|
||||||
|
cr1_clear:
|
||||||
|
.word 0x0120c302
|
||||||
|
cr1_set:
|
||||||
|
.word 0x00c0387d
|
||||||
|
|
||||||
|
__v7_setup_stack:
|
||||||
|
.space 4 * 11 @ 11 registers
|
||||||
|
|
||||||
|
.type v7_processor_functions, #object
|
||||||
|
ENTRY(v7_processor_functions)
|
||||||
|
.word v7_early_abort
|
||||||
|
.word cpu_v7_proc_init
|
||||||
|
.word cpu_v7_proc_fin
|
||||||
|
.word cpu_v7_reset
|
||||||
|
.word cpu_v7_do_idle
|
||||||
|
.word cpu_v7_dcache_clean_area
|
||||||
|
.word cpu_v7_switch_mm
|
||||||
|
.word cpu_v7_set_pte_ext
|
||||||
|
.size v7_processor_functions, . - v7_processor_functions
|
||||||
|
|
||||||
|
.type cpu_arch_name, #object
|
||||||
|
cpu_arch_name:
|
||||||
|
.asciz "armv7"
|
||||||
|
.size cpu_arch_name, . - cpu_arch_name
|
||||||
|
|
||||||
|
.type cpu_elf_name, #object
|
||||||
|
cpu_elf_name:
|
||||||
|
.asciz "v7"
|
||||||
|
.size cpu_elf_name, . - cpu_elf_name
|
||||||
|
.align
|
||||||
|
|
||||||
|
.section ".proc.info.init", #alloc, #execinstr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Match any ARMv7 processor core.
|
||||||
|
*/
|
||||||
|
.type __v7_proc_info, #object
|
||||||
|
__v7_proc_info:
|
||||||
|
.long 0x000f0000 @ Required ID value
|
||||||
|
.long 0x000f0000 @ Mask for ID
|
||||||
|
.long PMD_TYPE_SECT | \
|
||||||
|
PMD_SECT_BUFFERABLE | \
|
||||||
|
PMD_SECT_CACHEABLE | \
|
||||||
|
PMD_SECT_AP_WRITE | \
|
||||||
|
PMD_SECT_AP_READ
|
||||||
|
.long PMD_TYPE_SECT | \
|
||||||
|
PMD_SECT_XN | \
|
||||||
|
PMD_SECT_AP_WRITE | \
|
||||||
|
PMD_SECT_AP_READ
|
||||||
|
b __v7_setup
|
||||||
|
.long cpu_arch_name
|
||||||
|
.long cpu_elf_name
|
||||||
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
||||||
|
.long cpu_v7_name
|
||||||
|
.long v7_processor_functions
|
||||||
|
.long v6wbi_tlb_fns
|
||||||
|
.long v6_user_fns
|
||||||
|
.long v7_cache_fns
|
||||||
|
.size __v7_proc_info, . - __v7_proc_info
|
||||||
|
|
@ -102,6 +102,14 @@
|
||||||
//# endif
|
//# endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_CPU_V7)
|
||||||
|
//# ifdef _CACHE
|
||||||
|
# define MULTI_CACHE 1
|
||||||
|
//# else
|
||||||
|
//# define _CACHE v7
|
||||||
|
//# endif
|
||||||
|
#endif
|
||||||
|
|
||||||
#if !defined(_CACHE) && !defined(MULTI_CACHE)
|
#if !defined(_CACHE) && !defined(MULTI_CACHE)
|
||||||
#error Unknown cache maintainence model
|
#error Unknown cache maintainence model
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -38,6 +38,7 @@
|
||||||
* v5tej_early - ARMv5 with Thumb and Java early abort handler
|
* v5tej_early - ARMv5 with Thumb and Java early abort handler
|
||||||
* xscale - ARMv5 with Thumb with Xscale extensions
|
* xscale - ARMv5 with Thumb with Xscale extensions
|
||||||
* v6_early - ARMv6 generic early abort handler
|
* v6_early - ARMv6 generic early abort handler
|
||||||
|
* v7_early - ARMv7 generic early abort handler
|
||||||
*/
|
*/
|
||||||
#undef CPU_ABORT_HANDLER
|
#undef CPU_ABORT_HANDLER
|
||||||
#undef MULTI_ABORT
|
#undef MULTI_ABORT
|
||||||
|
|
@ -106,6 +107,14 @@
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_CPU_ABRT_EV7
|
||||||
|
# ifdef CPU_ABORT_HANDLER
|
||||||
|
# define MULTI_ABORT 1
|
||||||
|
# else
|
||||||
|
# define CPU_ABORT_HANDLER v7_early_abort
|
||||||
|
# endif
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifndef CPU_ABORT_HANDLER
|
#ifndef CPU_ABORT_HANDLER
|
||||||
#error Unknown data abort handler type
|
#error Unknown data abort handler type
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -193,6 +193,14 @@
|
||||||
# define CPU_NAME cpu_v6
|
# define CPU_NAME cpu_v6
|
||||||
# endif
|
# endif
|
||||||
# endif
|
# endif
|
||||||
|
# ifdef CONFIG_CPU_V7
|
||||||
|
# ifdef CPU_NAME
|
||||||
|
# undef MULTI_CPU
|
||||||
|
# define MULTI_CPU
|
||||||
|
# else
|
||||||
|
# define CPU_NAME cpu_v7
|
||||||
|
# endif
|
||||||
|
# endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
|
|
|
||||||
|
|
@ -14,6 +14,7 @@
|
||||||
#define CPU_ARCH_ARMv5TE 6
|
#define CPU_ARCH_ARMv5TE 6
|
||||||
#define CPU_ARCH_ARMv5TEJ 7
|
#define CPU_ARCH_ARMv5TEJ 7
|
||||||
#define CPU_ARCH_ARMv6 8
|
#define CPU_ARCH_ARMv6 8
|
||||||
|
#define CPU_ARCH_ARMv7 9
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* CR1 bits (CP#15 CR1)
|
* CR1 bits (CP#15 CR1)
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue