mirror of https://gitee.com/openkylin/linux.git
drm/amd/pp: Clean up powerplay code on Vega12
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
031ec948a8
commit
bbfcc8af37
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@ -48,7 +48,6 @@
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#include "pp_overdriver.h"
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#include "pp_thermal.h"
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static const ULONG PhwVega12_Magic = (ULONG)(PHM_VIslands_Magic);
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static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, uint32_t mask);
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@ -57,26 +56,6 @@ static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
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PPCLK_e clock_select,
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bool max);
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struct vega12_power_state *cast_phw_vega12_power_state(
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struct pp_hw_power_state *hw_ps)
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{
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PP_ASSERT_WITH_CODE((PhwVega12_Magic == hw_ps->magic),
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"Invalid Powerstate Type!",
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return NULL;);
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return (struct vega12_power_state *)hw_ps;
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}
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const struct vega12_power_state *cast_const_phw_vega12_power_state(
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const struct pp_hw_power_state *hw_ps)
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{
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PP_ASSERT_WITH_CODE((PhwVega12_Magic == hw_ps->magic),
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"Invalid Powerstate Type!",
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return NULL;);
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return (const struct vega12_power_state *)hw_ps;
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}
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static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
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{
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struct vega12_hwmgr *data =
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@ -590,7 +569,7 @@ static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
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}
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vega12_init_dpm_state(&(dpm_table->dpm_state));
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/* Initialize Mclk DPM table based on allow Mclk values */
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/* Initialize Mclk DPM table based on allow Mclk values */
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dpm_table = &(data->dpm_table.mem_table);
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PP_ASSERT_WITH_CODE(vega12_get_number_dpm_level(hwmgr, PPCLK_UCLK,
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@ -953,262 +932,12 @@ static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
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return result;
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}
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static int vega12_get_power_state_size(struct pp_hwmgr *hwmgr)
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{
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return sizeof(struct vega12_power_state);
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}
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static int vega12_get_number_of_pp_table_entries(struct pp_hwmgr *hwmgr)
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{
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return 0;
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}
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static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
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struct pp_hw_power_state *hw_ps)
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{
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return 0;
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}
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static int vega12_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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struct pp_power_state *request_ps,
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const struct pp_power_state *current_ps)
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{
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struct vega12_power_state *vega12_ps =
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cast_phw_vega12_power_state(&request_ps->hardware);
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uint32_t sclk;
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uint32_t mclk;
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struct PP_Clocks minimum_clocks = {0};
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bool disable_mclk_switching;
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bool disable_mclk_switching_for_frame_lock;
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bool disable_mclk_switching_for_vr;
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bool force_mclk_high;
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struct cgs_display_info info = {0};
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const struct phm_clock_and_voltage_limits *max_limits;
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uint32_t i;
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struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
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struct phm_ppt_v2_information *table_info =
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(struct phm_ppt_v2_information *)(hwmgr->pptable);
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int32_t count;
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uint32_t stable_pstate_sclk_dpm_percentage;
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uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
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uint32_t latency;
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data->battery_state = (PP_StateUILabel_Battery ==
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request_ps->classification.ui_label);
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if (vega12_ps->performance_level_count != 2)
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pr_info("VI should always have 2 performance levels");
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max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
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&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
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&(hwmgr->dyn_state.max_clock_voltage_on_dc);
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/* Cap clock DPM tables at DC MAX if it is in DC. */
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if (PP_PowerSource_DC == hwmgr->power_source) {
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for (i = 0; i < vega12_ps->performance_level_count; i++) {
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if (vega12_ps->performance_levels[i].mem_clock >
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max_limits->mclk)
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vega12_ps->performance_levels[i].mem_clock =
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max_limits->mclk;
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if (vega12_ps->performance_levels[i].gfx_clock >
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max_limits->sclk)
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vega12_ps->performance_levels[i].gfx_clock =
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max_limits->sclk;
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}
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}
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cgs_get_active_displays_info(hwmgr->device, &info);
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/* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
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minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock;
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minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock;
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if (PP_CAP(PHM_PlatformCaps_StablePState)) {
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PP_ASSERT_WITH_CODE(
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data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
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data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
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"percent sclk value must range from 1% to 100%, setting default value",
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stable_pstate_sclk_dpm_percentage = 75);
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max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
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stable_pstate_sclk = (max_limits->sclk *
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stable_pstate_sclk_dpm_percentage) / 100;
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for (count = table_info->vdd_dep_on_sclk->count - 1;
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count >= 0; count--) {
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if (stable_pstate_sclk >=
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table_info->vdd_dep_on_sclk->entries[count].clk) {
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stable_pstate_sclk =
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table_info->vdd_dep_on_sclk->entries[count].clk;
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break;
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}
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}
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if (count < 0)
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stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
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stable_pstate_mclk = max_limits->mclk;
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minimum_clocks.engineClock = stable_pstate_sclk;
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minimum_clocks.memoryClock = stable_pstate_mclk;
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}
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disable_mclk_switching_for_frame_lock = phm_cap_enabled(
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hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
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disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
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force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
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if (info.display_count == 0)
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disable_mclk_switching = false;
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else
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disable_mclk_switching = (info.display_count > 1) ||
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disable_mclk_switching_for_frame_lock ||
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disable_mclk_switching_for_vr ||
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force_mclk_high;
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sclk = vega12_ps->performance_levels[0].gfx_clock;
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mclk = vega12_ps->performance_levels[0].mem_clock;
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if (sclk < minimum_clocks.engineClock)
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sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
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max_limits->sclk : minimum_clocks.engineClock;
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if (mclk < minimum_clocks.memoryClock)
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mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
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max_limits->mclk : minimum_clocks.memoryClock;
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vega12_ps->performance_levels[0].gfx_clock = sclk;
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vega12_ps->performance_levels[0].mem_clock = mclk;
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if (vega12_ps->performance_levels[1].gfx_clock <
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vega12_ps->performance_levels[0].gfx_clock)
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vega12_ps->performance_levels[0].gfx_clock =
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vega12_ps->performance_levels[1].gfx_clock;
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if (disable_mclk_switching) {
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/* Set Mclk the max of level 0 and level 1 */
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if (mclk < vega12_ps->performance_levels[1].mem_clock)
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mclk = vega12_ps->performance_levels[1].mem_clock;
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/* Find the lowest MCLK frequency that is within
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* the tolerable latency defined in DAL
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*/
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latency = 0;
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for (i = 0; i < data->mclk_latency_table.count; i++) {
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if ((data->mclk_latency_table.entries[i].latency <= latency) &&
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(data->mclk_latency_table.entries[i].frequency >=
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vega12_ps->performance_levels[0].mem_clock) &&
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(data->mclk_latency_table.entries[i].frequency <=
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vega12_ps->performance_levels[1].mem_clock))
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mclk = data->mclk_latency_table.entries[i].frequency;
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}
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vega12_ps->performance_levels[0].mem_clock = mclk;
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} else {
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if (vega12_ps->performance_levels[1].mem_clock <
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vega12_ps->performance_levels[0].mem_clock)
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vega12_ps->performance_levels[0].mem_clock =
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vega12_ps->performance_levels[1].mem_clock;
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}
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if (PP_CAP(PHM_PlatformCaps_StablePState)) {
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for (i = 0; i < vega12_ps->performance_level_count; i++) {
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vega12_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
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vega12_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
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}
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}
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return 0;
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}
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static int vega12_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
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{
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struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
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struct PP_Clocks min_clocks = {0};
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struct cgs_display_info info = {0};
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data->need_update_dpm_table = 0;
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min_clocks.engineClockInSR = hwmgr->display_config.min_core_set_clock_in_sr;
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if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR &&
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(min_clocks.engineClockInSR >= VEGA12_MINIMUM_ENGINE_CLOCK ||
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data->display_timing.min_clock_in_sr >= VEGA12_MINIMUM_ENGINE_CLOCK))
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data->need_update_dpm_table |= DPMTABLE_UPDATE_SCLK;
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cgs_get_active_displays_info(hwmgr->device, &info);
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if (data->display_timing.num_existing_displays != info.display_count)
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data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
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return 0;
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}
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static int vega12_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
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struct vega12_single_dpm_table *dpm_table,
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uint32_t low_limit, uint32_t high_limit)
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{
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uint32_t i;
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for (i = 0; i < dpm_table->count; i++) {
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if ((dpm_table->dpm_levels[i].value < low_limit) ||
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(dpm_table->dpm_levels[i].value > high_limit))
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dpm_table->dpm_levels[i].enabled = false;
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else
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dpm_table->dpm_levels[i].enabled = true;
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}
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return 0;
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}
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static int vega12_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
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struct vega12_single_dpm_table *dpm_table,
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uint32_t low_limit, uint32_t high_limit,
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uint32_t disable_dpm_mask)
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{
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uint32_t i;
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for (i = 0; i < dpm_table->count; i++) {
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if ((dpm_table->dpm_levels[i].value < low_limit) ||
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(dpm_table->dpm_levels[i].value > high_limit))
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dpm_table->dpm_levels[i].enabled = false;
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else if ((!((1 << i) & disable_dpm_mask)) &&
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!(low_limit == high_limit))
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dpm_table->dpm_levels[i].enabled = false;
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else
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dpm_table->dpm_levels[i].enabled = true;
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}
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return 0;
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}
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static int vega12_trim_dpm_states(struct pp_hwmgr *hwmgr,
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const struct vega12_power_state *vega12_ps)
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{
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struct vega12_hwmgr *data =
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(struct vega12_hwmgr *)(hwmgr->backend);
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uint32_t high_limit_count;
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PP_ASSERT_WITH_CODE((vega12_ps->performance_level_count >= 1),
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"power state did not have any performance level",
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return -1);
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high_limit_count = (vega12_ps->performance_level_count == 1) ? 0 : 1;
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vega12_trim_single_dpm_states(hwmgr,
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&(data->dpm_table.soc_table),
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vega12_ps->performance_levels[0].soc_clock,
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vega12_ps->performance_levels[high_limit_count].soc_clock);
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vega12_trim_single_dpm_states_with_mask(hwmgr,
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&(data->dpm_table.gfx_table),
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vega12_ps->performance_levels[0].gfx_clock,
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vega12_ps->performance_levels[high_limit_count].gfx_clock,
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data->disable_dpm_mask);
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vega12_trim_single_dpm_states(hwmgr,
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&(data->dpm_table.mem_table),
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vega12_ps->performance_levels[0].mem_clock,
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vega12_ps->performance_levels[high_limit_count].mem_clock);
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return 0;
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}
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static uint32_t vega12_find_lowest_dpm_level(
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struct vega12_single_dpm_table *table)
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{
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@ -1250,45 +979,6 @@ static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
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return 0;
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}
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static int vega12_generate_dpm_level_enable_mask(
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struct pp_hwmgr *hwmgr, const void *input)
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{
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struct vega12_hwmgr *data =
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(struct vega12_hwmgr *)(hwmgr->backend);
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const struct phm_set_power_state_input *states =
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(const struct phm_set_power_state_input *)input;
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const struct vega12_power_state *vega12_ps =
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cast_const_phw_vega12_power_state(states->pnew_state);
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int i;
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PP_ASSERT_WITH_CODE(!vega12_trim_dpm_states(hwmgr, vega12_ps),
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"Attempt to Trim DPM States Failed!",
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return -1);
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data->smc_state_table.gfx_boot_level =
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vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
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data->smc_state_table.gfx_max_level =
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vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
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data->smc_state_table.mem_boot_level =
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vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
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data->smc_state_table.mem_max_level =
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vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
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PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
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"Attempt to upload DPM Bootup Levels Failed!",
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return -1);
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PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
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"Attempt to upload DPM Max Levels Failed!",
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return -1);
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for (i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
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data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
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for (i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
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data->dpm_table.mem_table.dpm_levels[i].enabled = true;
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return 0;
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}
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int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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@ -1307,45 +997,6 @@ int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
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return 0;
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}
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static int vega12_update_sclk_threshold(struct pp_hwmgr *hwmgr)
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{
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return 0;
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}
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static int vega12_set_power_state_tasks(struct pp_hwmgr *hwmgr,
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const void *input)
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{
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int tmp_result, result = 0;
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struct vega12_hwmgr *data =
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(struct vega12_hwmgr *)(hwmgr->backend);
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PPTable_t *pp_table = &(data->smc_state_table.pp_table);
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tmp_result = vega12_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
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PP_ASSERT_WITH_CODE(!tmp_result,
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"Failed to find DPM states clocks in DPM table!",
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result = tmp_result);
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tmp_result = vega12_generate_dpm_level_enable_mask(hwmgr, input);
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PP_ASSERT_WITH_CODE(!tmp_result,
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"Failed to generate DPM level enabled mask!",
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result = tmp_result);
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tmp_result = vega12_update_sclk_threshold(hwmgr);
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PP_ASSERT_WITH_CODE(!tmp_result,
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"Failed to update SCLK threshold!",
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result = tmp_result);
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result = vega12_copy_table_to_smc(hwmgr,
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(uint8_t *)pp_table, TABLE_PPTABLE);
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PP_ASSERT_WITH_CODE(!result,
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"Failed to upload PPtable!", return result);
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data->apply_optimized_settings = false;
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data->apply_overdrive_next_settings_mask = 0;
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return 0;
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}
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|
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static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
|
||||
{
|
||||
struct vega12_hwmgr *data =
|
||||
|
@ -2217,50 +1868,6 @@ static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
|
|||
vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
|
||||
}
|
||||
|
||||
static inline bool vega12_are_power_levels_equal(
|
||||
const struct vega12_performance_level *pl1,
|
||||
const struct vega12_performance_level *pl2)
|
||||
{
|
||||
return ((pl1->soc_clock == pl2->soc_clock) &&
|
||||
(pl1->gfx_clock == pl2->gfx_clock) &&
|
||||
(pl1->mem_clock == pl2->mem_clock));
|
||||
}
|
||||
|
||||
static int vega12_check_states_equal(struct pp_hwmgr *hwmgr,
|
||||
const struct pp_hw_power_state *pstate1,
|
||||
const struct pp_hw_power_state *pstate2, bool *equal)
|
||||
{
|
||||
const struct vega12_power_state *psa;
|
||||
const struct vega12_power_state *psb;
|
||||
int i;
|
||||
|
||||
if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
psa = cast_const_phw_vega12_power_state(pstate1);
|
||||
psb = cast_const_phw_vega12_power_state(pstate2);
|
||||
/* If the two states don't even have the same number of performance levels they cannot be the same state. */
|
||||
if (psa->performance_level_count != psb->performance_level_count) {
|
||||
*equal = false;
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < psa->performance_level_count; i++) {
|
||||
if (!vega12_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
|
||||
/* If we have found even one performance level pair that is different the states are different. */
|
||||
*equal = false;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
|
||||
*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
|
||||
*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
|
||||
*equal &= (psa->sclk_threshold == psb->sclk_threshold);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool
|
||||
vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
|
@ -2337,37 +1944,6 @@ static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
|
|||
static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
|
||||
struct amd_pp_profile *request)
|
||||
{
|
||||
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
|
||||
uint32_t sclk_idx = ~0, mclk_idx = ~0;
|
||||
|
||||
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
|
||||
return -EINVAL;
|
||||
|
||||
vega12_find_min_clock_index(hwmgr, &sclk_idx, &mclk_idx,
|
||||
request->min_sclk, request->min_mclk);
|
||||
|
||||
if (sclk_idx != ~0) {
|
||||
if (!data->registry_data.sclk_dpm_key_disabled)
|
||||
PP_ASSERT_WITH_CODE(
|
||||
!smum_send_msg_to_smc_with_parameter(
|
||||
hwmgr,
|
||||
PPSMC_MSG_SetSoftMinGfxclkByIndex,
|
||||
sclk_idx),
|
||||
"Failed to set soft min sclk index!",
|
||||
return -EINVAL);
|
||||
}
|
||||
|
||||
if (mclk_idx != ~0) {
|
||||
if (!data->registry_data.mclk_dpm_key_disabled)
|
||||
PP_ASSERT_WITH_CODE(
|
||||
!smum_send_msg_to_smc_with_parameter(
|
||||
hwmgr,
|
||||
PPSMC_MSG_SetSoftMinUclkByIndex,
|
||||
mclk_idx),
|
||||
"Failed to set soft min mclk index!",
|
||||
return -EINVAL);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -2389,28 +1965,6 @@ static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
|
|||
|
||||
static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
|
||||
{
|
||||
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
|
||||
struct vega12_single_dpm_table *golden_sclk_table =
|
||||
&(data->golden_dpm_table.gfx_table);
|
||||
struct pp_power_state *ps;
|
||||
struct vega12_power_state *vega12_ps;
|
||||
|
||||
ps = hwmgr->request_ps;
|
||||
|
||||
if (ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
vega12_ps = cast_phw_vega12_power_state(&ps->hardware);
|
||||
|
||||
vega12_ps->performance_levels[vega12_ps->performance_level_count - 1].gfx_clock =
|
||||
golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value / 100 +
|
||||
golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
|
||||
|
||||
if (vega12_ps->performance_levels[vega12_ps->performance_level_count - 1].gfx_clock >
|
||||
hwmgr->platform_descriptor.overdriveLimit.engineClock)
|
||||
vega12_ps->performance_levels[vega12_ps->performance_level_count - 1].gfx_clock =
|
||||
hwmgr->platform_descriptor.overdriveLimit.engineClock;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -2435,34 +1989,6 @@ static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
|
|||
|
||||
static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
|
||||
{
|
||||
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
|
||||
struct vega12_single_dpm_table *golden_mclk_table =
|
||||
&(data->golden_dpm_table.mem_table);
|
||||
struct pp_power_state *ps;
|
||||
struct vega12_power_state *vega12_ps;
|
||||
|
||||
ps = hwmgr->request_ps;
|
||||
|
||||
if (ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
vega12_ps = cast_phw_vega12_power_state(&ps->hardware);
|
||||
|
||||
vega12_ps->performance_levels
|
||||
[vega12_ps->performance_level_count - 1].mem_clock =
|
||||
golden_mclk_table->dpm_levels
|
||||
[golden_mclk_table->count - 1].value *
|
||||
value / 100 +
|
||||
golden_mclk_table->dpm_levels
|
||||
[golden_mclk_table->count - 1].value;
|
||||
|
||||
if (vega12_ps->performance_levels
|
||||
[vega12_ps->performance_level_count - 1].mem_clock >
|
||||
hwmgr->platform_descriptor.overdriveLimit.memoryClock)
|
||||
vega12_ps->performance_levels
|
||||
[vega12_ps->performance_level_count - 1].mem_clock =
|
||||
hwmgr->platform_descriptor.overdriveLimit.memoryClock;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
@ -2514,12 +2040,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
|
|||
.asic_setup = vega12_setup_asic_task,
|
||||
.dynamic_state_management_enable = vega12_enable_dpm_tasks,
|
||||
.dynamic_state_management_disable = vega12_disable_dpm_tasks,
|
||||
.get_num_of_pp_table_entries =
|
||||
vega12_get_number_of_pp_table_entries,
|
||||
.get_power_state_size = vega12_get_power_state_size,
|
||||
.patch_boot_state = vega12_patch_boot_state,
|
||||
.apply_state_adjust_rules = vega12_apply_state_adjust_rules,
|
||||
.power_state_set = vega12_set_power_state_tasks,
|
||||
.get_sclk = vega12_dpm_get_sclk,
|
||||
.get_mclk = vega12_dpm_get_mclk,
|
||||
.notify_smc_display_config_after_ps_adjustment =
|
||||
|
@ -2543,7 +2064,6 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
|
|||
.display_config_changed = vega12_display_configuration_changed_task,
|
||||
.powergate_uvd = vega12_power_gate_uvd,
|
||||
.powergate_vce = vega12_power_gate_vce,
|
||||
.check_states_equal = vega12_check_states_equal,
|
||||
.check_smc_update_required_for_display_configuration =
|
||||
vega12_check_smc_update_required_for_display_configuration,
|
||||
.power_off_asic = vega12_power_off_asic,
|
||||
|
|
|
@ -86,37 +86,6 @@ struct smu_features {
|
|||
uint64_t smu_feature_bitmap;
|
||||
};
|
||||
|
||||
struct vega12_performance_level {
|
||||
uint32_t soc_clock;
|
||||
uint32_t gfx_clock;
|
||||
uint32_t mem_clock;
|
||||
};
|
||||
|
||||
struct vega12_bacos {
|
||||
uint32_t baco_flags;
|
||||
/* struct vega12_performance_level performance_level; */
|
||||
};
|
||||
|
||||
struct vega12_uvd_clocks {
|
||||
uint32_t vclk;
|
||||
uint32_t dclk;
|
||||
};
|
||||
|
||||
struct vega12_vce_clocks {
|
||||
uint32_t evclk;
|
||||
uint32_t ecclk;
|
||||
};
|
||||
|
||||
struct vega12_power_state {
|
||||
uint32_t magic;
|
||||
struct vega12_uvd_clocks uvd_clks;
|
||||
struct vega12_vce_clocks vce_clks;
|
||||
uint16_t performance_level_count;
|
||||
bool dc_compatible;
|
||||
uint32_t sclk_threshold;
|
||||
struct vega12_performance_level performance_levels[VEGA12_MAX_HARDWARE_POWERLEVELS];
|
||||
};
|
||||
|
||||
struct vega12_dpm_level {
|
||||
bool enabled;
|
||||
uint32_t value;
|
||||
|
@ -350,7 +319,6 @@ struct vega12_hwmgr {
|
|||
|
||||
uint32_t active_auto_throttle_sources;
|
||||
uint32_t water_marks_bitmap;
|
||||
struct vega12_bacos bacos;
|
||||
|
||||
struct vega12_odn_dpm_table odn_dpm_table;
|
||||
struct vega12_odn_fan_table odn_fan_table;
|
||||
|
|
Loading…
Reference in New Issue