mirror of https://gitee.com/openkylin/linux.git
drm/radeon: update power state parsing for CI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1945,6 +1945,7 @@ union pplib_clock_info {
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struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
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struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
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struct _ATOM_PPLIB_SI_CLOCK_INFO si;
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struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
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};
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union pplib_power_state {
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@ -2353,6 +2354,15 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
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sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
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rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
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}
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} else if (rdev->family >= CHIP_BONAIRE) {
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sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
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sclk |= clock_info->ci.ucEngineClockHigh << 16;
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mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
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mclk |= clock_info->ci.ucMemoryClockHigh << 16;
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rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
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rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
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rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
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VOLTAGE_NONE;
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} else if (rdev->family >= CHIP_TAHITI) {
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sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
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sclk |= clock_info->si.ucEngineClockHigh << 16;
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