mirror of https://gitee.com/openkylin/linux.git
net/at91_ether: use macb register definitions
Use register and bits definitions from the macb header. This makes it possible to have one header file for this hardware. Process was scripted and the resulting object file has the same checksum. Signed-off-by: Joachim Eastwood <manabian@gmail.com>
This commit is contained in:
Joachim Eastwood
David S. Miller
parent
1fd3ca4e14
commit
bc3bbef690
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@ -36,11 +36,11 @@
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#include <asm/uaccess.h>
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#include <asm/mach-types.h>
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#include <mach/at91rm9200_emac.h>
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#include <asm/gpio.h>
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#include <mach/board.h>
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#include "at91_ether.h"
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#include "macb.h"
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#define DRV_NAME "at91_ether"
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#define DRV_VERSION "1.0"
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@ -76,8 +76,8 @@ static void enable_mdi(struct at91_private *lp)
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{
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unsigned long ctl;
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ctl = at91_emac_read(lp, AT91_EMAC_CTL);
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at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
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ctl = at91_emac_read(lp, MACB_NCR);
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at91_emac_write(lp, MACB_NCR, ctl | MACB_BIT(MPE)); /* enable management port */
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}
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/*
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@ -87,8 +87,8 @@ static void disable_mdi(struct at91_private *lp)
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{
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unsigned long ctl;
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ctl = at91_emac_read(lp, AT91_EMAC_CTL);
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at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
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ctl = at91_emac_read(lp, MACB_NCR);
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at91_emac_write(lp, MACB_NCR, ctl & ~MACB_BIT(MPE)); /* disable management port */
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}
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/*
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@ -98,7 +98,7 @@ static inline void at91_phy_wait(struct at91_private *lp)
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{
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unsigned long timeout = jiffies + 2;
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while (!(at91_emac_read(lp, AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
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while (!(at91_emac_read(lp, MACB_NSR) & MACB_BIT(IDLE))) {
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if (time_after(jiffies, timeout)) {
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printk("at91_ether: MIO timeout\n");
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break;
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@ -113,8 +113,9 @@ static inline void at91_phy_wait(struct at91_private *lp)
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*/
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static void write_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int value)
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{
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at91_emac_write(lp, AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
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| ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
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at91_emac_write(lp, MACB_MAN, MACB_BF(SOF, MACB_MAN_SOF) | MACB_BF(CODE, MACB_MAN_CODE)
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| MACB_BF(RW, MACB_MAN_WRITE) | ((phy_addr & 0x1f) << 23)
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| (address << 18) | (value & ((1<<MACB_DATA_SIZE) - 1)));
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/* Wait until IDLE bit in Network Status register is cleared */
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at91_phy_wait(lp);
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@ -126,13 +127,14 @@ static void write_phy(struct at91_private *lp, unsigned char phy_addr, unsigned
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*/
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static void read_phy(struct at91_private *lp, unsigned char phy_addr, unsigned char address, unsigned int *value)
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{
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at91_emac_write(lp, AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
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| ((phy_addr & 0x1f) << 23) | (address << 18));
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at91_emac_write(lp, MACB_MAN, MACB_BF(SOF, MACB_MAN_SOF) | MACB_BF(CODE, MACB_MAN_CODE)
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| MACB_BF(RW, MACB_MAN_READ) | ((phy_addr & 0x1f) << 23)
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| (address << 18));
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/* Wait until IDLE bit in Network Status register is cleared */
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at91_phy_wait(lp);
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*value = at91_emac_read(lp, AT91_EMAC_MAN) & AT91_EMAC_DATA;
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*value = at91_emac_read(lp, MACB_MAN) & ((1<<MACB_DATA_SIZE) - 1);
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}
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/* ........................... PHY MANAGEMENT .......................... */
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@ -173,18 +175,18 @@ static void update_linkspeed(struct net_device *dev, int silent)
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}
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/* Update the MAC */
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mac_cfg = at91_emac_read(lp, AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
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mac_cfg = at91_emac_read(lp, MACB_NCFGR) & ~(MACB_BIT(SPD) | MACB_BIT(FD));
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if (speed == SPEED_100) {
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if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
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mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
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mac_cfg |= MACB_BIT(SPD) | MACB_BIT(FD);
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else /* 100 Half Duplex */
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mac_cfg |= AT91_EMAC_SPD;
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mac_cfg |= MACB_BIT(SPD);
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} else {
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if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
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mac_cfg |= AT91_EMAC_FD;
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mac_cfg |= MACB_BIT(FD);
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else {} /* 10 Half Duplex */
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}
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at91_emac_write(lp, AT91_EMAC_CFG, mac_cfg);
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at91_emac_write(lp, MACB_NCFGR, mac_cfg);
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if (!silent)
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printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
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@ -479,16 +481,16 @@ static void __init get_mac_address(struct net_device *dev)
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struct at91_private *lp = netdev_priv(dev);
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/* Check Specific-Address 1 */
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if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA1H), at91_emac_read(lp, AT91_EMAC_SA1L)))
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if (unpack_mac_address(dev, at91_emac_read(lp, MACB_SA1T), at91_emac_read(lp, MACB_SA1B)))
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return;
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/* Check Specific-Address 2 */
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if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA2H), at91_emac_read(lp, AT91_EMAC_SA2L)))
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if (unpack_mac_address(dev, at91_emac_read(lp, MACB_SA2T), at91_emac_read(lp, MACB_SA2B)))
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return;
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/* Check Specific-Address 3 */
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if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA3H), at91_emac_read(lp, AT91_EMAC_SA3L)))
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if (unpack_mac_address(dev, at91_emac_read(lp, MACB_SA3T), at91_emac_read(lp, MACB_SA3B)))
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return;
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/* Check Specific-Address 4 */
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if (unpack_mac_address(dev, at91_emac_read(lp, AT91_EMAC_SA4H), at91_emac_read(lp, AT91_EMAC_SA4L)))
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if (unpack_mac_address(dev, at91_emac_read(lp, MACB_SA4T), at91_emac_read(lp, MACB_SA4B)))
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return;
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printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
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@ -501,11 +503,12 @@ static void update_mac_address(struct net_device *dev)
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{
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struct at91_private *lp = netdev_priv(dev);
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at91_emac_write(lp, AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
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at91_emac_write(lp, AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
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at91_emac_write(lp, MACB_SA1B, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16)
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| (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
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at91_emac_write(lp, MACB_SA1T, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
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at91_emac_write(lp, AT91_EMAC_SA2L, 0);
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at91_emac_write(lp, AT91_EMAC_SA2H, 0);
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at91_emac_write(lp, MACB_SA2B, 0);
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at91_emac_write(lp, MACB_SA2T, 0);
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}
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/*
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@ -597,8 +600,8 @@ static void at91ether_sethashtable(struct net_device *dev)
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mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
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}
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at91_emac_write(lp, AT91_EMAC_HSL, mc_filter[0]);
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at91_emac_write(lp, AT91_EMAC_HSH, mc_filter[1]);
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at91_emac_write(lp, MACB_HRB, mc_filter[0]);
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at91_emac_write(lp, MACB_HRT, mc_filter[1]);
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}
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/*
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@ -609,27 +612,27 @@ static void at91ether_set_multicast_list(struct net_device *dev)
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struct at91_private *lp = netdev_priv(dev);
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unsigned long cfg;
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cfg = at91_emac_read(lp, AT91_EMAC_CFG);
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cfg = at91_emac_read(lp, MACB_NCFGR);
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if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
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cfg |= AT91_EMAC_CAF;
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cfg |= MACB_BIT(CAF);
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else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
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cfg &= ~AT91_EMAC_CAF;
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cfg &= ~MACB_BIT(CAF);
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if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
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at91_emac_write(lp, AT91_EMAC_HSH, -1);
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at91_emac_write(lp, AT91_EMAC_HSL, -1);
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cfg |= AT91_EMAC_MTI;
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at91_emac_write(lp, MACB_HRT, -1);
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at91_emac_write(lp, MACB_HRB, -1);
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cfg |= MACB_BIT(NCFGR_MTI);
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} else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */
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at91ether_sethashtable(dev);
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cfg |= AT91_EMAC_MTI;
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cfg |= MACB_BIT(NCFGR_MTI);
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} else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
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at91_emac_write(lp, AT91_EMAC_HSH, 0);
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at91_emac_write(lp, AT91_EMAC_HSL, 0);
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cfg &= ~AT91_EMAC_MTI;
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at91_emac_write(lp, MACB_HRT, 0);
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at91_emac_write(lp, MACB_HRB, 0);
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cfg &= ~MACB_BIT(NCFGR_MTI);
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}
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at91_emac_write(lp, AT91_EMAC_CFG, cfg);
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at91_emac_write(lp, MACB_NCFGR, cfg);
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}
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/* ......................... ETHTOOL SUPPORT ........................... */
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@ -762,11 +765,11 @@ static void at91ether_start(struct net_device *dev)
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lp->rxBuffIndex = 0;
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/* Program address of descriptor list in Rx Buffer Queue register */
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at91_emac_write(lp, AT91_EMAC_RBQP, (unsigned long) dlist_phys);
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at91_emac_write(lp, MACB_RBQP, (unsigned long) dlist_phys);
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/* Enable Receive and Transmit */
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ctl = at91_emac_read(lp, AT91_EMAC_CTL);
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at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
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ctl = at91_emac_read(lp, MACB_NCR);
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at91_emac_write(lp, MACB_NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
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}
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/*
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@ -783,8 +786,8 @@ static int at91ether_open(struct net_device *dev)
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clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
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/* Clear internal statistics */
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ctl = at91_emac_read(lp, AT91_EMAC_CTL);
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at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
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ctl = at91_emac_read(lp, MACB_NCR);
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at91_emac_write(lp, MACB_NCR, ctl | MACB_BIT(CLRSTAT));
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/* Update the MAC address (incase user has changed it) */
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update_mac_address(dev);
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@ -793,9 +796,9 @@ static int at91ether_open(struct net_device *dev)
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enable_phyirq(dev);
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/* Enable MAC interrupts */
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at91_emac_write(lp, AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
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| AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
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| AT91_EMAC_ROVR | AT91_EMAC_ABT);
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at91_emac_write(lp, MACB_IER, MACB_BIT(RCOMP) | MACB_BIT(RXUBR)
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| MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE) | MACB_BIT(TCOMP)
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| MACB_BIT(ISR_ROVR) | MACB_BIT(HRESP));
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/* Determine current link speed */
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spin_lock_irq(&lp->lock);
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@ -818,16 +821,17 @@ static int at91ether_close(struct net_device *dev)
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unsigned long ctl;
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/* Disable Receiver and Transmitter */
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ctl = at91_emac_read(lp, AT91_EMAC_CTL);
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at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
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ctl = at91_emac_read(lp, MACB_NCR);
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at91_emac_write(lp, MACB_NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
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/* Disable PHY interrupt */
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disable_phyirq(dev);
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/* Disable MAC interrupts */
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at91_emac_write(lp, AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
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| AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
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| AT91_EMAC_ROVR | AT91_EMAC_ABT);
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at91_emac_write(lp, MACB_IDR, MACB_BIT(RCOMP) | MACB_BIT(RXUBR)
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| MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)
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| MACB_BIT(TCOMP) | MACB_BIT(ISR_ROVR)
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| MACB_BIT(HRESP));
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netif_stop_queue(dev);
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@ -843,7 +847,7 @@ static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct at91_private *lp = netdev_priv(dev);
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if (at91_emac_read(lp, AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
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if (at91_emac_read(lp, MACB_TSR) & MACB_BIT(RM9200_BNQ)) {
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netif_stop_queue(dev);
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/* Store packet information (to free when Tx completed) */
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@ -853,9 +857,9 @@ static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
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dev->stats.tx_bytes += skb->len;
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/* Set address of the data in the Transmit Address register */
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at91_emac_write(lp, AT91_EMAC_TAR, lp->skb_physaddr);
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at91_emac_write(lp, MACB_TAR, lp->skb_physaddr);
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/* Set length of the packet in the Transmit Control register */
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at91_emac_write(lp, AT91_EMAC_TCR, skb->len);
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at91_emac_write(lp, MACB_TCR, skb->len);
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} else {
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printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
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@ -876,28 +880,28 @@ static struct net_device_stats *at91ether_stats(struct net_device *dev)
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int ale, lenerr, seqe, lcol, ecol;
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if (netif_running(dev)) {
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dev->stats.rx_packets += at91_emac_read(lp, AT91_EMAC_OK); /* Good frames received */
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ale = at91_emac_read(lp, AT91_EMAC_ALE);
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dev->stats.rx_packets += at91_emac_read(lp, MACB_FRO); /* Good frames received */
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ale = at91_emac_read(lp, MACB_ALE);
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dev->stats.rx_frame_errors += ale; /* Alignment errors */
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lenerr = at91_emac_read(lp, AT91_EMAC_ELR) + at91_emac_read(lp, AT91_EMAC_USF);
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lenerr = at91_emac_read(lp, MACB_ELE) + at91_emac_read(lp, MACB_USF);
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dev->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
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seqe = at91_emac_read(lp, AT91_EMAC_SEQE);
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seqe = at91_emac_read(lp, MACB_FCSE);
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dev->stats.rx_crc_errors += seqe; /* CRC error */
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dev->stats.rx_fifo_errors += at91_emac_read(lp, AT91_EMAC_DRFC);/* Receive buffer not available */
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dev->stats.rx_fifo_errors += at91_emac_read(lp, MACB_RRE);/* Receive buffer not available */
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dev->stats.rx_errors += (ale + lenerr + seqe
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+ at91_emac_read(lp, AT91_EMAC_CDE) + at91_emac_read(lp, AT91_EMAC_RJB));
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+ at91_emac_read(lp, MACB_RSE) + at91_emac_read(lp, MACB_RJA));
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dev->stats.tx_packets += at91_emac_read(lp, AT91_EMAC_FRA); /* Frames successfully transmitted */
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dev->stats.tx_fifo_errors += at91_emac_read(lp, AT91_EMAC_TUE); /* Transmit FIFO underruns */
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dev->stats.tx_carrier_errors += at91_emac_read(lp, AT91_EMAC_CSE); /* Carrier Sense errors */
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dev->stats.tx_heartbeat_errors += at91_emac_read(lp, AT91_EMAC_SQEE);/* Heartbeat error */
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dev->stats.tx_packets += at91_emac_read(lp, MACB_FTO); /* Frames successfully transmitted */
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dev->stats.tx_fifo_errors += at91_emac_read(lp, MACB_TUND); /* Transmit FIFO underruns */
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dev->stats.tx_carrier_errors += at91_emac_read(lp, MACB_CSE); /* Carrier Sense errors */
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dev->stats.tx_heartbeat_errors += at91_emac_read(lp, MACB_STE);/* Heartbeat error */
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lcol = at91_emac_read(lp, AT91_EMAC_LCOL);
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ecol = at91_emac_read(lp, AT91_EMAC_ECOL);
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lcol = at91_emac_read(lp, MACB_LCOL);
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ecol = at91_emac_read(lp, MACB_EXCOL);
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dev->stats.tx_window_errors += lcol; /* Late collisions */
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dev->stats.tx_aborted_errors += ecol; /* 16 collisions */
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dev->stats.collisions += (at91_emac_read(lp, AT91_EMAC_SCOL) + at91_emac_read(lp, AT91_EMAC_MCOL) + lcol + ecol);
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dev->stats.collisions += (at91_emac_read(lp, MACB_SCF) + at91_emac_read(lp, MACB_MCF) + lcol + ecol);
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}
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return &dev->stats;
|
||||
}
|
||||
|
|
@ -954,14 +958,14 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
|
|||
|
||||
/* MAC Interrupt Status register indicates what interrupts are pending.
|
||||
It is automatically cleared once read. */
|
||||
intstatus = at91_emac_read(lp, AT91_EMAC_ISR);
|
||||
intstatus = at91_emac_read(lp, MACB_ISR);
|
||||
|
||||
if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
|
||||
if (intstatus & MACB_BIT(RCOMP)) /* Receive complete */
|
||||
at91ether_rx(dev);
|
||||
|
||||
if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
|
||||
if (intstatus & MACB_BIT(TCOMP)) { /* Transmit complete */
|
||||
/* The TCOM bit is set even if the transmission failed. */
|
||||
if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
|
||||
if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
|
||||
dev->stats.tx_errors += 1;
|
||||
|
||||
if (lp->skb) {
|
||||
|
|
@ -973,13 +977,13 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
|
|||
}
|
||||
|
||||
/* Work-around for Errata #11 */
|
||||
if (intstatus & AT91_EMAC_RBNA) {
|
||||
ctl = at91_emac_read(lp, AT91_EMAC_CTL);
|
||||
at91_emac_write(lp, AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
|
||||
at91_emac_write(lp, AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
|
||||
if (intstatus & MACB_BIT(RXUBR)) {
|
||||
ctl = at91_emac_read(lp, MACB_NCR);
|
||||
at91_emac_write(lp, MACB_NCR, ctl & ~MACB_BIT(RE));
|
||||
at91_emac_write(lp, MACB_NCR, ctl | MACB_BIT(RE));
|
||||
}
|
||||
|
||||
if (intstatus & AT91_EMAC_ROVR)
|
||||
if (intstatus & MACB_BIT(ISR_ROVR))
|
||||
printk("%s: ROVR error\n", dev->name);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
|
@ -1114,12 +1118,12 @@ static int __init at91ether_probe(struct platform_device *pdev)
|
|||
get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
|
||||
update_mac_address(dev); /* Program ethernet address into MAC */
|
||||
|
||||
at91_emac_write(lp, AT91_EMAC_CTL, 0);
|
||||
at91_emac_write(lp, MACB_NCR, 0);
|
||||
|
||||
if (board_data->is_rmii)
|
||||
at91_emac_write(lp, AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
|
||||
at91_emac_write(lp, MACB_NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG) | MACB_BIT(RM9200_RMII));
|
||||
else
|
||||
at91_emac_write(lp, AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
|
||||
at91_emac_write(lp, MACB_NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
|
||||
|
||||
/* Detect PHY */
|
||||
if (!at91ether_phy_detect(lp)) {
|
||||
|
|
@ -1163,8 +1167,8 @@ static int __init at91ether_probe(struct platform_device *pdev)
|
|||
/* Display ethernet banner */
|
||||
printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
|
||||
dev->name, (uint) dev->base_addr, dev->irq,
|
||||
at91_emac_read(lp, AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
|
||||
at91_emac_read(lp, AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
|
||||
at91_emac_read(lp, MACB_NCFGR) & MACB_BIT(SPD) ? "100-" : "10-",
|
||||
at91_emac_read(lp, MACB_NCFGR) & MACB_BIT(FD) ? "FullDuplex" : "HalfDuplex",
|
||||
dev->dev_addr);
|
||||
if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
|
||||
printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
|
||||
|
|
|
|||
Loading…
Reference in New Issue