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x86-64/smp: fix random SIGSEGV issues 

They seem to have been due to AMD errata 63/122; the fix is to disable
TLB flush filtering in SMP configurations.

Confirmed to fix the problem by Andrew Walrond <andrew@walrond.org>

[ Let's see if we'll have a better fix eventually, this is the Q&D
  "let's get this fixed and out there" version ]

Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Linus Torvalds 2005-09-17 15:41:04 -07:00
parent 61ffcafafb
commit bc5e8fdfc6
1 changed files with 15 additions and 0 deletions
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15
arch/x86_64/kernel/setup.c
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@ -831,11 +831,26 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
#endif #endif
} }
#define HWCR 0xc0010015
static int __init init_amd(struct cpuinfo_x86 *c) static int __init init_amd(struct cpuinfo_x86 *c)
{ {
int r; int r;
int level; int level;
#ifdef CONFIG_SMP
unsigned long value;
// Disable TLB flush filter by setting HWCR.FFDIS:
// bit 6 of msr C001_0015
//
// Errata 63 for SH-B3 steppings
// Errata 122 for all(?) steppings
rdmsrl(HWCR, value);
value |= 1 << 6;
wrmsrl(HWCR, value);
#endif
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID; /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
clear_bit(0*32+31, &c->x86_capability); clear_bit(0*32+31, &c->x86_capability);