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clk: tegra: Init cfg structure in _get_pll_mnp 

Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.

Based on work by  Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Peter De Schrijver 2017-07-25 13:34:06 +03:00 committed by Stephen Boyd
parent e34e69cc86
commit bc7b34a2fb
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/tegra/clk-pll.c
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@ -690,6 +690,8 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll,
struct tegra_clk_pll_params *params = pll->params;
struct div_nmp *div_nmp = params->div_nmp;
*cfg = (struct tegra_clk_pll_freq_table) { };
if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {