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ARM: dts: imx6qdl: add multiplexer controls 

The IOMUXC General Purpose Register space contains various bitfields
that control video bus multiplexers. Describe them using a mmio-mux
node. The placement of the IPU CSI video mux controls differs between
i.MX6D/Q and i.MX6S/DL.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Philipp Zabel 2017-06-12 11:23:54 -07:00 committed by Shawn Guo
parent cc20028f68
commit bc97e88ecd
3 changed files with 26 additions and 1 deletions
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10
arch/arm/boot/dts/imx6dl.dtsi
View File

@ -181,6 +181,16 @@ &ldb {
"di0", "di1";
};
&mux {
mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
<0x34 0x00000038>, /* IPU_CSI1_MUX */
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};

10
arch/arm/boot/dts/imx6q.dtsi
View File

@ -332,6 +332,16 @@ mipi_mux_3: endpoint {
};
};
&mux {
mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
<0x04 0x00100000>, /* MIPI_IPU2_MUX */
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
};
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};

7
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -826,8 +826,13 @@ pd_pu: power-domain@1 {
};
gpr: iomuxc-gpr@020e0000 {
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
reg = <0x020e0000 0x38>;
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
};
};
iomuxc: iomuxc@020e0000 {