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ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq support 

This adds some operating points for cpu frequeny scaling

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Matthew McClintock 2018-07-25 10:37:46 +02:00 committed by Andy Gross
parent 233c77d4f1
commit bcb9ab4c29
1 changed files with 26 additions and 28 deletions
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54
arch/arm/boot/dts/qcom-ipq4019.dtsi
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@ -59,14 +59,8 @@ cpu@0 {
reg = <0x0>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
operating-points = <
/* kHz uV (fixed) */
48000 1100000
200000 1100000
500000 1100000
716000 1100000
>;
clock-latency = <256000>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@1 {
@ -79,14 +73,8 @@ cpu@1 {
reg = <0x1>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
operating-points = <
/* kHz uV (fixed) */
48000 1100000
200000 1100000
500000 1100000
666000 1100000
>;
clock-latency = <256000>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@2 {
@ -99,14 +87,8 @@ cpu@2 {
reg = <0x2>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
operating-points = <
/* kHz uV (fixed) */
48000 1100000
200000 1100000
500000 1100000
666000 1100000
>;
clock-latency = <256000>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@3 {
@ -119,14 +101,8 @@ cpu@3 {
reg = <0x3>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
operating-points = <
/* kHz uV (fixed) */
48000 1100000
200000 1100000
500000 1100000
666000 1100000
>;
clock-latency = <256000>;
operating-points-v2 = <&cpu0_opp_table>;
};
L2: l2-cache {
@ -135,6 +111,28 @@ L2: l2-cache {
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-48000000 {
opp-hz = /bits/ 64 <48000000>;
clock-latency-ns = <256000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
clock-latency-ns = <256000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <256000>;
};
opp-716000000 {
opp-hz = /bits/ 64 <716000000>;
clock-latency-ns = <256000>;
};
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |