mirror of https://gitee.com/openkylin/linux.git
Fixes for omaps for v5.4-rc cycle
Here are fixes for omaps to deal with few regressions, and to fix more boot time errors and warnings: - The recent ti-sysc interconnect target module driver changes had incorrect clock bits for both clocks and dts that cause warnings - For omap3-gta04, gpio changes caused the LCD to break a while back, and after discussing things the right fix is to set spi-cs-high - Recent omapdrm changes to use generic panels caused tfp410 to be disabled as we now must enable the generic support for it in defconfig - Recent omapdrm and backlight changes also finally made droid4 LCD to work, so let's enable it in the defconfig it can be used out of the box. This is not strictly a fix, but we still also have the older CONFIG_MFD_TI_LMU options available so this cuts down the confusion for trying to guess which display and which backlight is needed - Recent ti-sysc interconnect target module changes need the gpio module disabled on some boards, but this now needs to happen at the module level, not at the gpio driver level - Recent changes to probe system timers with ti-sysc caused warnings about mismatch in syconfig registers, so let's configure the option for RESET_STATUS as available in the TRMs - Recent changes to probe LCDC with ti-sysc caused warnings about mismatch in sysconfig registers, so let's configure the missing idlemodes for both platform data and dts as documented in TRMs - Since we moved mach-omap2 to probe with device tree, we've been getting voltage controller warnings. Turns out this code is no longer needed, so let's just remove omap2_set_init_voltage() to get rid of the pointless warnings - Configure am4372 dispc memory bandwidth to avoid underflow errors -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl2U6fcRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXMu5RAAi9bqFTwKU3YiA4o0yDufGtx63fMziCD4 pMct5DMqyIfkCbU6KIp/pC3g3x35zl7WjoAbyB9Q8o33g/9mnQUSSTkB1TID/fZ0 +d7epXsGPRWymP2B13xOH/yRJv8dDeVWVHLBJdatuaAJ0mygpf4a4ChkXYKp+nhl oShxeRiOYYCrhowklmjvzV0atz17QSNc42GvAUpL3aicU9XmeYn7JLcxZ+3dBXuz 5IRbM/kt66i0owT6Oymf2lvf+UXELLXL/bXINPbPyYrXw94WuIk1z3i3gtQLsRk+ CyoYczBsgSWZRoFJB03324HY+KhGNHbC6kjfqoWk5UrbbX13L1+tSnKSlFRcZddx 64HPZISsgPOlx+i4TlTw/7YMq6FbLB8Z9gp+J1hxycynjYrfVQNCJADMlQDqA1DS gncdaz0O1RVcQULndFu7EYyLvybUjFmr0Q1wrW7mOFbIQn7KVTNYJ9GUJjWwmYcI N9yw6H7FjNad0TA+5prXKvQj+iP6budedW9Ke3mvyhkePMKwvORX5I6aVKjL0vKo gjUKuZC2x75GxgiUwYIJwDOEQGkBySFtf7RGFBjJ7l73/r4kDH6X/kG5AQDB0l3e sTSgMTM8KbkNWdQsvATSEN0Tf4Z7UsuhAhKLihNmkt7YXaYXEtBu0xoKPR8y6Xbd ZkiGMxkpLUY= =SkMF -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.4/fixes-rc1-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes Fixes for omaps for v5.4-rc cycle Here are fixes for omaps to deal with few regressions, and to fix more boot time errors and warnings: - The recent ti-sysc interconnect target module driver changes had incorrect clock bits for both clocks and dts that cause warnings - For omap3-gta04, gpio changes caused the LCD to break a while back, and after discussing things the right fix is to set spi-cs-high - Recent omapdrm changes to use generic panels caused tfp410 to be disabled as we now must enable the generic support for it in defconfig - Recent omapdrm and backlight changes also finally made droid4 LCD to work, so let's enable it in the defconfig it can be used out of the box. This is not strictly a fix, but we still also have the older CONFIG_MFD_TI_LMU options available so this cuts down the confusion for trying to guess which display and which backlight is needed - Recent ti-sysc interconnect target module changes need the gpio module disabled on some boards, but this now needs to happen at the module level, not at the gpio driver level - Recent changes to probe system timers with ti-sysc caused warnings about mismatch in syconfig registers, so let's configure the option for RESET_STATUS as available in the TRMs - Recent changes to probe LCDC with ti-sysc caused warnings about mismatch in sysconfig registers, so let's configure the missing idlemodes for both platform data and dts as documented in TRMs - Since we moved mach-omap2 to probe with device tree, we've been getting voltage controller warnings. Turns out this code is no longer needed, so let's just remove omap2_set_init_voltage() to get rid of the pointless warnings - Configure am4372 dispc memory bandwidth to avoid underflow errors * tag 'omap-for-v5.4/fixes-rc1-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am4372: Set memory bandwidth limit for DISPC ARM: OMAP2+: Fix warnings with broken omap2_set_init_voltage() ARM: OMAP2+: Add missing LCDC midlemode for am335x ARM: OMAP2+: Fix missing reset done flag for am3 and am43 ARM: dts: Fix gpio0 flags for am335x-icev2 ARM: omap2plus_defconfig: Enable more droid4 devices as loadable modules ARM: omap2plus_defconfig: Enable DRM_TI_TFP410 DTS: ARM: gta04: introduce legacy spi-cs-high to make display work again ARM: dts: Fix wrong clocks for dra7 mcasp clk: ti: dra7: Fix mcasp8 clock bits Link: https://lore.kernel.org/r/pull-1570040410-308159@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
bcec1221c9
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@ -432,7 +432,7 @@ &mmc1 {
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pinctrl-0 = <&mmc0_pins_default>;
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};
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&gpio0 {
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&gpio0_target {
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/* Do not idle the GPIO used for holding the VTT regulator */
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ti,no-reset-on-init;
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ti,no-idle-on-init;
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@ -127,7 +127,7 @@ target-module@5000 { /* 0x44e05000, ap 12 30.0 */
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ranges = <0x0 0x5000 0x1000>;
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};
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target-module@7000 { /* 0x44e07000, ap 14 20.0 */
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gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
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compatible = "ti,sysc-omap2", "ti,sysc";
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ti,hwmods = "gpio1";
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reg = <0x7000 0x4>,
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@ -2038,7 +2038,9 @@ target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
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reg = <0xe000 0x4>,
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<0xe054 0x4>;
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reg-names = "rev", "sysc";
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ti,sysc-midle ;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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@ -337,6 +337,8 @@ dispc: dispc@4832a400 {
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ti,hwmods = "dss_dispc";
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clocks = <&disp_clk>;
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clock-names = "fck";
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max-memory-bandwidth = <230000000>;
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};
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rfbi: rfbi@4832a800 {
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@ -2732,7 +2732,7 @@ mcasp1: mcasp@0 {
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interrupt-names = "tx", "rx";
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dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
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dma-names = "tx", "rx";
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clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>,
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clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
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<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
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<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
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clock-names = "fck", "ahclkx", "ahclkr";
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@ -2768,8 +2768,8 @@ mcasp2: mcasp@0 {
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interrupt-names = "tx", "rx";
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dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
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dma-names = "tx", "rx";
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
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<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
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clock-names = "fck", "ahclkx", "ahclkr";
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status = "disabled";
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@ -2786,9 +2786,8 @@ target-module@68000 { /* 0x48468000, ap 13 26.0 */
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<SYSC_IDLE_SMART>;
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/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>;
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clock-names = "fck", "ahclkx", "ahclkr";
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<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x68000 0x2000>,
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@ -2804,7 +2803,7 @@ mcasp3: mcasp@0 {
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interrupt-names = "tx", "rx";
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dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
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dma-names = "tx", "rx";
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>,
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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status = "disabled";
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@ -2821,9 +2820,8 @@ target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
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<SYSC_IDLE_SMART>;
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/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>;
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clock-names = "fck", "ahclkx", "ahclkr";
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<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x6c000 0x2000>,
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@ -2839,7 +2837,7 @@ mcasp4: mcasp@0 {
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interrupt-names = "tx", "rx";
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dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
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dma-names = "tx", "rx";
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>,
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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status = "disabled";
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@ -2856,9 +2854,8 @@ target-module@70000 { /* 0x48470000, ap 19 36.0 */
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<SYSC_IDLE_SMART>;
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/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>;
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clock-names = "fck", "ahclkx", "ahclkr";
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<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x70000 0x2000>,
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@ -2874,7 +2871,7 @@ mcasp5: mcasp@0 {
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interrupt-names = "tx", "rx";
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dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
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dma-names = "tx", "rx";
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>,
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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status = "disabled";
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@ -2891,9 +2888,8 @@ target-module@74000 { /* 0x48474000, ap 35 14.0 */
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<SYSC_IDLE_SMART>;
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/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>;
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clock-names = "fck", "ahclkx", "ahclkr";
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<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x74000 0x2000>,
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@ -2909,7 +2905,7 @@ mcasp6: mcasp@0 {
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interrupt-names = "tx", "rx";
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dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
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dma-names = "tx", "rx";
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>,
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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status = "disabled";
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@ -2926,9 +2922,8 @@ target-module@78000 { /* 0x48478000, ap 39 0c.0 */
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<SYSC_IDLE_SMART>;
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/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>;
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clock-names = "fck", "ahclkx", "ahclkr";
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<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x78000 0x2000>,
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@ -2944,7 +2939,7 @@ mcasp7: mcasp@0 {
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interrupt-names = "tx", "rx";
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dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
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dma-names = "tx", "rx";
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>,
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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status = "disabled";
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@ -2961,9 +2956,8 @@ target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
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<SYSC_IDLE_SMART>;
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/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>;
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clock-names = "fck", "ahclkx", "ahclkr";
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<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x7c000 0x2000>,
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@ -2979,7 +2973,7 @@ mcasp8: mcasp@0 {
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interrupt-names = "tx", "rx";
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dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
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dma-names = "tx", "rx";
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>,
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clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
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<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
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clock-names = "fck", "ahclkx";
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status = "disabled";
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@ -124,6 +124,7 @@ lcd: td028ttec1@0 {
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spi-max-frequency = <100000>;
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spi-cpol;
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spi-cpha;
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spi-cs-high;
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backlight= <&backlight>;
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label = "lcd";
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@ -364,6 +364,7 @@ CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
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CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
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CONFIG_DRM_TILCDC=m
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CONFIG_DRM_PANEL_SIMPLE=m
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CONFIG_DRM_TI_TFP410=m
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CONFIG_FB=y
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CONFIG_FIRMWARE_EDID=y
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CONFIG_FB_MODE_HELPERS=y
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@ -423,6 +424,7 @@ CONFIG_USB_SERIAL_GENERIC=y
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CONFIG_USB_SERIAL_SIMPLE=m
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CONFIG_USB_SERIAL_FTDI_SIO=m
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CONFIG_USB_SERIAL_PL2303=m
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CONFIG_USB_SERIAL_OPTION=m
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CONFIG_USB_TEST=m
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CONFIG_NOP_USB_XCEIV=m
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CONFIG_AM335X_PHY_USB=m
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@ -460,6 +462,7 @@ CONFIG_MMC_SDHCI_OMAP=y
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CONFIG_NEW_LEDS=y
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CONFIG_LEDS_CLASS=m
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CONFIG_LEDS_CPCAP=m
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CONFIG_LEDS_LM3532=m
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CONFIG_LEDS_GPIO=m
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CONFIG_LEDS_PCA963X=m
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CONFIG_LEDS_PWM=m
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@ -763,7 +763,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
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.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSC_HAS_RESET_STATUS,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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@ -231,8 +231,9 @@ static struct omap_hwmod am33xx_control_hwmod = {
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static struct omap_hwmod_class_sysconfig lcdc_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x54,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
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.idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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|
|
@ -74,83 +74,6 @@ int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This API is to be called during init to set the various voltage
|
||||
* domains to the voltage as per the opp table. Typically we boot up
|
||||
* at the nominal voltage. So this function finds out the rate of
|
||||
* the clock associated with the voltage domain, finds out the correct
|
||||
* opp entry and sets the voltage domain to the voltage specified
|
||||
* in the opp entry
|
||||
*/
|
||||
static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
|
||||
const char *oh_name)
|
||||
{
|
||||
struct voltagedomain *voltdm;
|
||||
struct clk *clk;
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long freq, bootup_volt;
|
||||
struct device *dev;
|
||||
|
||||
if (!vdd_name || !clk_name || !oh_name) {
|
||||
pr_err("%s: invalid parameters\n", __func__);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (!strncmp(oh_name, "mpu", 3))
|
||||
/*
|
||||
* All current OMAPs share voltage rail and clock
|
||||
* source, so CPU0 is used to represent the MPU-SS.
|
||||
*/
|
||||
dev = get_cpu_device(0);
|
||||
else
|
||||
dev = omap_device_get_by_hwmod_name(oh_name);
|
||||
|
||||
if (IS_ERR(dev)) {
|
||||
pr_err("%s: Unable to get dev pointer for hwmod %s\n",
|
||||
__func__, oh_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
voltdm = voltdm_lookup(vdd_name);
|
||||
if (!voltdm) {
|
||||
pr_err("%s: unable to get vdd pointer for vdd_%s\n",
|
||||
__func__, vdd_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
clk = clk_get(NULL, clk_name);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
freq = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
|
||||
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
|
||||
if (IS_ERR(opp)) {
|
||||
pr_err("%s: unable to find boot up OPP for vdd_%s\n",
|
||||
__func__, vdd_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
bootup_volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
if (!bootup_volt) {
|
||||
pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
|
||||
__func__, vdd_name);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
voltdm_scale(voltdm, bootup_volt);
|
||||
return 0;
|
||||
|
||||
exit:
|
||||
pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SUSPEND
|
||||
static int omap_pm_enter(suspend_state_t suspend_state)
|
||||
{
|
||||
|
|
@ -208,25 +131,6 @@ void omap_common_suspend_init(void *pm_suspend)
|
|||
}
|
||||
#endif /* CONFIG_SUSPEND */
|
||||
|
||||
static void __init omap3_init_voltages(void)
|
||||
{
|
||||
if (!soc_is_omap34xx())
|
||||
return;
|
||||
|
||||
omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
|
||||
omap2_set_init_voltage("core", "l3_ick", "l3_main");
|
||||
}
|
||||
|
||||
static void __init omap4_init_voltages(void)
|
||||
{
|
||||
if (!soc_is_omap44xx())
|
||||
return;
|
||||
|
||||
omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
|
||||
omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
|
||||
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
|
||||
}
|
||||
|
||||
int __maybe_unused omap_pm_nop_init(void)
|
||||
{
|
||||
return 0;
|
||||
|
|
@ -246,10 +150,6 @@ int __init omap2_common_pm_late_init(void)
|
|||
omap4_twl_init();
|
||||
omap_voltage_late_init();
|
||||
|
||||
/* Initialize the voltages */
|
||||
omap3_init_voltages();
|
||||
omap4_init_voltages();
|
||||
|
||||
/* Smartreflex device init */
|
||||
omap_devinit_smartreflex();
|
||||
|
||||
|
|
|
|||
|
|
@ -683,7 +683,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst
|
|||
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
|
||||
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
|
||||
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
|
||||
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" },
|
||||
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
|
||||
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
|
||||
{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
|
||||
{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
|
||||
|
|
@ -828,8 +828,8 @@ static struct ti_dt_clk dra7xx_clks[] = {
|
|||
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
|
||||
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
|
||||
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
|
||||
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"),
|
||||
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"),
|
||||
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
|
||||
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
|
||||
DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
|
||||
DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
|
||||
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
|
||||
|
|
|
|||
Loading…
Reference in New Issue