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drm/nvc0: support for sw methods + enable page flipping 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2011-02-08 15:16:23 +10:00
parent d7117e0d4e
commit bd2f2037a4
3 changed files with 23 additions and 7 deletions
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10
drivers/gpu/drm/nouveau/nouveau_display.c
View File

@ -224,6 +224,7 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
struct nouveau_page_flip_state *s, struct nouveau_page_flip_state *s,
struct nouveau_fence **pfence) struct nouveau_fence **pfence)
{ {
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
struct drm_device *dev = chan->dev; struct drm_device *dev = chan->dev;
unsigned long flags; unsigned long flags;
int ret; int ret;
@ -243,9 +244,12 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
if (ret) if (ret)
goto fail; goto fail;
BEGIN_RING(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); if (dev_priv->card_type < NV_C0)
OUT_RING(chan, 0); BEGIN_RING(chan, NvSubSw, NV_SW_PAGE_FLIP, 1);
FIRE_RING(chan); else
BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0500, 1);
OUT_RING (chan, 0);
FIRE_RING (chan);
ret = nouveau_fence_new(chan, pfence, true); ret = nouveau_fence_new(chan, pfence, true);
if (ret) if (ret)

2
drivers/gpu/drm/nouveau/nouveau_state.c
View File

@ -1118,7 +1118,7 @@ int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
getparam->value = 1; getparam->value = 1;
break; break;
case NOUVEAU_GETPARAM_HAS_PAGEFLIP: case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
getparam->value = (dev_priv->card_type < NV_C0) ? 1 : 0; getparam->value = 1;
break; break;
case NOUVEAU_GETPARAM_GRAPH_UNITS: case NOUVEAU_GETPARAM_GRAPH_UNITS:
/* NV40 and NV50 versions are quite different, but register /* NV40 and NV50 versions are quite different, but register

18
drivers/gpu/drm/nouveau/nvc0_graph.c
View File

@ -298,6 +298,14 @@ nvc0_graph_takedown(struct drm_device *dev)
nvc0_graph_destroy(dev); nvc0_graph_destroy(dev);
} }
static int
nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
u32 class, u32 mthd, u32 data)
{
nouveau_finish_page_flip(chan, NULL);
return 0;
}
static int static int
nvc0_graph_create(struct drm_device *dev) nvc0_graph_create(struct drm_device *dev)
{ {
@ -395,6 +403,7 @@ nvc0_graph_create(struct drm_device *dev)
nouveau_irq_register(dev, 25, nvc0_runk140_isr); nouveau_irq_register(dev, 25, nvc0_runk140_isr);
NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */ NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */ NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */ NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
return 0; return 0;
@ -728,9 +737,12 @@ nvc0_graph_isr(struct drm_device *dev)
u32 class = nv_rd32(dev, 0x404200 + (subc * 4)); u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
if (stat & 0x00000010) { if (stat & 0x00000010) {
NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] subc %d " if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
"class 0x%04x mthd 0x%04x data 0x%08x\n", NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
chid, inst, subc, class, mthd, data); "subc %d class 0x%04x mthd 0x%04x "
"data 0x%08x\n",
chid, inst, subc, class, mthd, data);
}
nv_wr32(dev, 0x400100, 0x00000010); nv_wr32(dev, 0x400100, 0x00000010);
stat &= ~0x00000010; stat &= ~0x00000010;
} }