mirror of https://gitee.com/openkylin/linux.git
[media] media: i2c: adv7604: Use v4l2-dv-timings helpers
Use the helper to enumerate and set DV timings instead of a custom code. This will ease debugging too, as it is consistent with other drivers. Signed-off-by: Jean-Michel Hautbois <jean-michel.hautbois@veo-labs.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Jean-Michel Hautbois
Mauro Carvalho Chehab
parent
b292394d4f
commit
bd3e275f3e
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@ -207,71 +207,22 @@ static bool adv76xx_has_afe(struct adv76xx_state *state)
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return state->info->has_afe;
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}
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/* Supported CEA and DMT timings */
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static const struct v4l2_dv_timings adv76xx_timings[] = {
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V4L2_DV_BT_CEA_720X480P59_94,
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V4L2_DV_BT_CEA_720X576P50,
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V4L2_DV_BT_CEA_1280X720P24,
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V4L2_DV_BT_CEA_1280X720P25,
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V4L2_DV_BT_CEA_1280X720P50,
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V4L2_DV_BT_CEA_1280X720P60,
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V4L2_DV_BT_CEA_1920X1080P24,
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V4L2_DV_BT_CEA_1920X1080P25,
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V4L2_DV_BT_CEA_1920X1080P30,
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V4L2_DV_BT_CEA_1920X1080P50,
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V4L2_DV_BT_CEA_1920X1080P60,
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/* sorted by DMT ID */
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V4L2_DV_BT_DMT_640X350P85,
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V4L2_DV_BT_DMT_640X400P85,
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V4L2_DV_BT_DMT_720X400P85,
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V4L2_DV_BT_DMT_640X480P60,
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V4L2_DV_BT_DMT_640X480P72,
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V4L2_DV_BT_DMT_640X480P75,
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V4L2_DV_BT_DMT_640X480P85,
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V4L2_DV_BT_DMT_800X600P56,
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V4L2_DV_BT_DMT_800X600P60,
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V4L2_DV_BT_DMT_800X600P72,
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V4L2_DV_BT_DMT_800X600P75,
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V4L2_DV_BT_DMT_800X600P85,
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V4L2_DV_BT_DMT_848X480P60,
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V4L2_DV_BT_DMT_1024X768P60,
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V4L2_DV_BT_DMT_1024X768P70,
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V4L2_DV_BT_DMT_1024X768P75,
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V4L2_DV_BT_DMT_1024X768P85,
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V4L2_DV_BT_DMT_1152X864P75,
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V4L2_DV_BT_DMT_1280X768P60_RB,
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V4L2_DV_BT_DMT_1280X768P60,
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V4L2_DV_BT_DMT_1280X768P75,
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V4L2_DV_BT_DMT_1280X768P85,
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V4L2_DV_BT_DMT_1280X800P60_RB,
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V4L2_DV_BT_DMT_1280X800P60,
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V4L2_DV_BT_DMT_1280X800P75,
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V4L2_DV_BT_DMT_1280X800P85,
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V4L2_DV_BT_DMT_1280X960P60,
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V4L2_DV_BT_DMT_1280X960P85,
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V4L2_DV_BT_DMT_1280X1024P60,
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V4L2_DV_BT_DMT_1280X1024P75,
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V4L2_DV_BT_DMT_1280X1024P85,
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V4L2_DV_BT_DMT_1360X768P60,
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V4L2_DV_BT_DMT_1400X1050P60_RB,
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V4L2_DV_BT_DMT_1400X1050P60,
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V4L2_DV_BT_DMT_1400X1050P75,
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V4L2_DV_BT_DMT_1400X1050P85,
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V4L2_DV_BT_DMT_1440X900P60_RB,
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V4L2_DV_BT_DMT_1440X900P60,
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V4L2_DV_BT_DMT_1600X1200P60,
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V4L2_DV_BT_DMT_1680X1050P60_RB,
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V4L2_DV_BT_DMT_1680X1050P60,
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V4L2_DV_BT_DMT_1792X1344P60,
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V4L2_DV_BT_DMT_1856X1392P60,
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V4L2_DV_BT_DMT_1920X1200P60_RB,
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V4L2_DV_BT_DMT_1366X768P60_RB,
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V4L2_DV_BT_DMT_1366X768P60,
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V4L2_DV_BT_DMT_1920X1080P60,
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{ },
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/* Unsupported timings. This device cannot support 720p30. */
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static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
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V4L2_DV_BT_CEA_1280X720P30,
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{ }
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};
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static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
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{
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int i;
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for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
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if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
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return false;
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return true;
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}
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struct adv76xx_video_standards {
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struct v4l2_dv_timings timings;
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u8 vid_std;
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@ -806,6 +757,36 @@ static inline bool is_digital_input(struct v4l2_subdev *sd)
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state->selected_input == ADV7604_PAD_HDMI_PORT_D;
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}
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static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
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.type = V4L2_DV_BT_656_1120,
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/* keep this initialization for compatibility with GCC < 4.4.6 */
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.reserved = { 0 },
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V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
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V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
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V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
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V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
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V4L2_DV_BT_CAP_CUSTOM)
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};
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static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
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.type = V4L2_DV_BT_656_1120,
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/* keep this initialization for compatibility with GCC < 4.4.6 */
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.reserved = { 0 },
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V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
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V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
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V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
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V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
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V4L2_DV_BT_CAP_CUSTOM)
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};
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static inline const struct v4l2_dv_timings_cap *
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adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd)
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{
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return is_digital_input(sd) ? &adv76xx_timings_cap_digital :
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&adv7604_timings_cap_analog;
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}
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/* ----------------------------------------------------------------------- */
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#ifdef CONFIG_VIDEO_ADV_DEBUG
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@ -1330,17 +1311,23 @@ static int stdi2dv_timings(struct v4l2_subdev *sd,
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u32 pix_clk;
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int i;
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for (i = 0; adv76xx_timings[i].bt.height; i++) {
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if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
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for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
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const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
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if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
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adv76xx_get_dv_timings_cap(sd),
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adv76xx_check_dv_timings, NULL))
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continue;
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if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
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if (vtotal(bt) != stdi->lcf + 1)
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continue;
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if (bt->vsync != stdi->lcvs)
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continue;
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pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
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pix_clk = hfreq * htotal(bt);
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if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
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(pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
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*timings = adv76xx_timings[i];
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if ((pix_clk < bt->pixelclock + 1000000) &&
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(pix_clk > bt->pixelclock - 1000000)) {
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*timings = v4l2_dv_timings_presets[i];
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return 0;
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}
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}
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@ -1425,15 +1412,11 @@ static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
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{
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struct adv76xx_state *state = to_state(sd);
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if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
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return -EINVAL;
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if (timings->pad >= state->source_pad)
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return -EINVAL;
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memset(timings->reserved, 0, sizeof(timings->reserved));
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timings->timings = adv76xx_timings[timings->index];
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return 0;
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return v4l2_enum_dv_timings_cap(timings,
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adv76xx_get_dv_timings_cap(sd), adv76xx_check_dv_timings, NULL);
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}
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static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
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@ -1444,29 +1427,7 @@ static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
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if (cap->pad >= state->source_pad)
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return -EINVAL;
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cap->type = V4L2_DV_BT_656_1120;
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cap->bt.max_width = 1920;
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cap->bt.max_height = 1200;
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cap->bt.min_pixelclock = 25000000;
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switch (cap->pad) {
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case ADV76XX_PAD_HDMI_PORT_A:
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case ADV7604_PAD_HDMI_PORT_B:
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case ADV7604_PAD_HDMI_PORT_C:
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case ADV7604_PAD_HDMI_PORT_D:
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cap->bt.max_pixelclock = 225000000;
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break;
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case ADV7604_PAD_VGA_RGB:
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case ADV7604_PAD_VGA_COMP:
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default:
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cap->bt.max_pixelclock = 170000000;
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break;
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}
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cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
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V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
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cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
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V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
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*cap = *adv76xx_get_dv_timings_cap(sd);
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return 0;
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}
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@ -1475,15 +1436,9 @@ static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
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static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
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struct v4l2_dv_timings *timings)
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{
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int i;
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for (i = 0; adv76xx_timings[i].bt.width; i++) {
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if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
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is_digital_input(sd) ? 250000 : 1000000, false)) {
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*timings = adv76xx_timings[i];
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break;
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}
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}
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v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd),
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is_digital_input(sd) ? 250000 : 1000000,
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adv76xx_check_dv_timings, NULL);
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}
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static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
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@ -1651,12 +1606,9 @@ static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
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bt = &timings->bt;
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if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
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(is_digital_input(sd) && bt->pixelclock > 225000000)) {
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v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
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__func__, (u32)bt->pixelclock);
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if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd),
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adv76xx_check_dv_timings, NULL))
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return -ERANGE;
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}
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adv76xx_fill_optional_dv_timings_fields(sd, timings);
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