mirror of https://gitee.com/openkylin/linux.git
Merge branch 'lorenzo/pci/armada8k'
- enable register clock for Armada 7K/8K (Gregory CLEMENT) * lorenzo/pci/armada8k: PCI: armada8k: Fix clock resource by adding a register clock PCI: armada8k: Remove useless test before clk_disable_unprepare()
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commit
bdc4bb1377
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@ -12,7 +12,10 @@ Required properties:
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- "ctrl" for the control register region
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- "config" for the config space region
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- interrupts: Interrupt specifier for the PCIe controler
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- clocks: reference to the PCIe controller clock
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- clocks: reference to the PCIe controller clocks
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- clock-names: mandatory if there is a second clock, in this case the
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name must be "core" for the first clock and "reg" for the second
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one
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Example:
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@ -28,6 +28,7 @@
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struct armada8k_pcie {
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struct dw_pcie *pci;
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struct clk *clk;
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struct clk *clk_reg;
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};
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#define PCIE_VENDOR_REGS_OFFSET 0x8000
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@ -229,26 +230,38 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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pcie->clk_reg = devm_clk_get(dev, "reg");
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if (pcie->clk_reg == ERR_PTR(-EPROBE_DEFER)) {
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ret = -EPROBE_DEFER;
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goto fail;
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}
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if (!IS_ERR(pcie->clk_reg)) {
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ret = clk_prepare_enable(pcie->clk_reg);
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if (ret)
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goto fail_clkreg;
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}
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/* Get the dw-pcie unit configuration/control registers base. */
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base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, base);
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if (IS_ERR(pci->dbi_base)) {
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dev_err(dev, "couldn't remap regs base %p\n", base);
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ret = PTR_ERR(pci->dbi_base);
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goto fail;
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goto fail_clkreg;
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}
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platform_set_drvdata(pdev, pcie);
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ret = armada8k_add_pcie_port(pcie, pdev);
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if (ret)
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goto fail;
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goto fail_clkreg;
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return 0;
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fail_clkreg:
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clk_disable_unprepare(pcie->clk_reg);
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fail:
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if (!IS_ERR(pcie->clk))
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clk_disable_unprepare(pcie->clk);
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clk_disable_unprepare(pcie->clk);
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return ret;
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}
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