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i.MX arm device tree update for 5.2: 

- New board support: imx50-kobo-aura, imx53-m53menlo, imx6dl-eckelmann,
    imx7d-mba7, imx7d-zii-rpu2, and vf610-zii-spb4.
  - Add i2c, mmc and spi aliases for SoC i.MX35, i.MX50 and i.MX6SL.
  - Use new 'reset-gpios' property describing CODEC reset pin for board
    mx6qdl-zii-rdu2, imx6qdl-gw5903 and imx6qdl-var-dart.
  - Specify viewport count for PCIE block on SoC imx7d and imx6qdl.
  - Correct 'ipg' clock of SDMA device for i.MX5, i.MX6 and i.MX7 SoCs.
  - Rename MMDC memory controller device to be generic and add MMDC
    device for imx7ulp SoC.
  - Add OCOTP device support for imx7ulp SoC.
  - Improve ZII board DTS by switching to SPDX identifier and using generic
    device node name.
  - A series from Rui Miguel Silva to add various media related devices
    for i.MX7 SoC, and enable ov2680 sensor support for imx7s-warp board.
  - Random small updates on various board support.
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Merge tag 'imx-dt-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm device tree update for 5.2:
 - New board support: imx50-kobo-aura, imx53-m53menlo, imx6dl-eckelmann,
   imx7d-mba7, imx7d-zii-rpu2, and vf610-zii-spb4.
 - Add i2c, mmc and spi aliases for SoC i.MX35, i.MX50 and i.MX6SL.
 - Use new 'reset-gpios' property describing CODEC reset pin for board
   mx6qdl-zii-rdu2, imx6qdl-gw5903 and imx6qdl-var-dart.
 - Specify viewport count for PCIE block on SoC imx7d and imx6qdl.
 - Correct 'ipg' clock of SDMA device for i.MX5, i.MX6 and i.MX7 SoCs.
 - Rename MMDC memory controller device to be generic and add MMDC
   device for imx7ulp SoC.
 - Add OCOTP device support for imx7ulp SoC.
 - Improve ZII board DTS by switching to SPDX identifier and using generic
   device node name.
 - A series from Rui Miguel Silva to add various media related devices
   for i.MX7 SoC, and enable ov2680 sensor support for imx7s-warp board.
 - Random small updates on various board support.

* tag 'imx-dt-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (59 commits)
  ARM: dts: imx7s: Specify #io-channel-cells in ADC nodes
  ARM: dts: vf610-zii-dev-rev-b: Specify CS as GPIO_ACTIVE_LOW in spi0
  ARM: dts: vf610-zii-dev: Mark i2c0 SCL as GPIO_OPEN_DRAIN
  ARM: dts: Add support for ZII i.MX7 RPU2 board
  ARM: dts: bugfix tqma7 soft reset issue
  ARM: dts: imx53: Add Menlosystems M53 board
  ARM: dts: imx53: Rename M53 SoM touchscreen node
  ARM: dts: imx6dl-sabreauto: update opp table for auto part
  ARM: dts: imx: Use generic node names for Zii dts
  ARM: dts: imx: Switch Zii dts to SPDX identifier
  ARM: dts: imx6q-logicpd: Shutdown LCD regulator during suspend
  ARM: dts: imx6q-logicpd: Enable Analog audio capture
  ARM: dts: imx6sll: add cooling-cells for cpu-freq cooling device
  ARM: dts: imx50: Add Kobo Aura DTS
  ARM: dts: imx6qdl-var-dart: Use new CODEC reset pin name
  ARM: dts: imx6qdl-gw5903: Use new CODEC reset pin name
  ARM: dts: mx6qdl-zii-rdu2: Use new CODEC reset pin name
  ARM: dts: imx50: Specify IMX5_CLK_IPG as "ahb" clock to SDMA
  ARM: dts: imx51: Specify IMX5_CLK_IPG as "ahb" clock to SDMA
  ARM: dts: imx53: Specify IMX5_CLK_IPG as "ahb" clock to SDMA
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-28 12:51:23 -07:00
parent b45da609a0 4171797ff7
commit be058ba65d
49 changed files with 3809 additions and 300 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/boot/dts/Makefile
View File

@ -363,7 +363,8 @@ dtb-$(CONFIG_SOC_IMX35) += \
imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-eukrea-mbimxsd35-baseboard.dtb \
imx35-pdk.dtb imx35-pdk.dtb
dtb-$(CONFIG_SOC_IMX50) += \ dtb-$(CONFIG_SOC_IMX50) += \
imx50-evk.dtb imx50-evk.dtb \
imx50-kobo-aura.dtb
dtb-$(CONFIG_SOC_IMX51) += \ dtb-$(CONFIG_SOC_IMX51) += \
imx51-apf51.dtb \ imx51-apf51.dtb \
imx51-apf51dev.dtb \ imx51-apf51dev.dtb \
@ -380,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-kp-ddc.dtb \ imx53-kp-ddc.dtb \
imx53-kp-hsc.dtb \ imx53-kp-hsc.dtb \
imx53-m53evk.dtb \ imx53-m53evk.dtb \
imx53-m53menlo.dtb \
imx53-mba53.dtb \ imx53-mba53.dtb \
imx53-ppd.dtb \ imx53-ppd.dtb \
imx53-qsb.dtb \ imx53-qsb.dtb \
@ -400,6 +402,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \
imx6dl-dfi-fs700-m60.dtb \ imx6dl-dfi-fs700-m60.dtb \
imx6dl-eckelmann-ci4x10.dtb \
imx6dl-emcon-avari.dtb \ imx6dl-emcon-avari.dtb \
imx6dl-gw51xx.dtb \ imx6dl-gw51xx.dtb \
imx6dl-gw52xx.dtb \ imx6dl-gw52xx.dtb \
@ -579,6 +582,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \ imx7d-cl-som-imx7.dtb \
imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \
imx7d-mba7.dtb \
imx7d-nitrogen7.dtb \ imx7d-nitrogen7.dtb \
imx7d-pico-hobbit.dtb \ imx7d-pico-hobbit.dtb \
imx7d-pico-pi.dtb \ imx7d-pico-pi.dtb \
@ -586,7 +590,9 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-sdb.dtb \ imx7d-sdb.dtb \
imx7d-sdb-reva.dtb \ imx7d-sdb-reva.dtb \
imx7d-sdb-sht11.dtb \ imx7d-sdb-sht11.dtb \
imx7d-zii-rpu2.dtb \
imx7s-colibri-eval-v3.dtb \ imx7s-colibri-eval-v3.dtb \
imx7s-mba7.dtb \
imx7s-warp.dtb imx7s-warp.dtb
dtb-$(CONFIG_SOC_IMX7ULP) += \ dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-evk.dtb imx7ulp-evk.dtb
@ -606,6 +612,7 @@ dtb-$(CONFIG_SOC_VF610) += \
vf610-zii-dev-rev-b.dtb \ vf610-zii-dev-rev-b.dtb \
vf610-zii-dev-rev-c.dtb \ vf610-zii-dev-rev-c.dtb \
vf610-zii-scu4-aib.dtb \ vf610-zii-scu4-aib.dtb \
vf610-zii-spb4.dtb \
vf610-zii-ssmb-dtu.dtb \ vf610-zii-ssmb-dtu.dtb \
vf610-zii-ssmb-spu3.dtb vf610-zii-ssmb-spu3.dtb
dtb-$(CONFIG_ARCH_MXS) += \ dtb-$(CONFIG_ARCH_MXS) += \

6
arch/arm/boot/dts/imx35.dtsi
View File

@ -21,6 +21,12 @@ aliases {
gpio0 = &gpio1; gpio0 = &gpio1;
gpio1 = &gpio2; gpio1 = &gpio2;
gpio2 = &gpio3; gpio2 = &gpio3;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
serial0 = &uart1; serial0 = &uart1;
serial1 = &uart2; serial1 = &uart2;
serial2 = &uart3; serial2 = &uart3;

258
arch/arm/boot/dts/imx50-kobo-aura.dts Normal file
View File

@ -0,0 +1,258 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright 2019 Jonathan Neuschäfer
//
// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B.
/dts-v1/;
#include "imx50.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Kobo Aura (N514)";
compatible = "kobo,aura", "fsl,imx50";
chosen {
stdout-path = "serial1:115200n8";
};
memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x10000000>;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
on {
label = "kobo_aura:orange:on";
gpios = <&gpio6 24 GPIO_ACTIVE_LOW>;
panic-indicator;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpiokeys>;
power {
label = "Power Button";
gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
};
hallsensor {
label = "Hallsensor";
gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESERVED>;
linux,input-type = <EV_SW>;
};
frontlight {
label = "Frontlight";
gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DISPLAYTOGGLE>;
};
};
sd2_pwrseq: pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_reset>;
reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
};
sd2_vmmc: gpio-regulator {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_vmmc>;
regulator-name = "vmmc";
states = <3300000 0>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>;
startup-delay-us = <100000>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd1>;
max-frequency = <50000000>;
bus-width = <4>;
cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
disable-wp;
status = "okay";
/* External µSD card */
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2>;
bus-width = <4>;
max-frequency = <50000000>;
disable-wp;
mmc-pwrseq = <&sd2_pwrseq>;
vmmc-supply = <&sd2_vmmc>;
status = "okay";
/* CyberTan WC121 SDIO WiFi (BCM43362) */
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd3>;
bus-width = <8>;
non-removable;
max-frequency = <50000000>;
disable-wp;
status = "okay";
/* Internal eMMC */
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
/* TODO: ektf2132 touch controller at 0x15 */
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
/* TODO: TPS65185 PMIC for E Ink at 0x68 */
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
/* TODO: embedded controller at 0x43 */
};
&iomuxc {
pinctrl_gpiokeys: gpiokeys {
fsl,pins = <
MX50_PAD_CSPI_MISO__GPIO4_10 0x0
MX50_PAD_SD2_D7__GPIO5_15 0x0
MX50_PAD_KEY_ROW0__GPIO4_1 0x0
>;
};
pinctrl_i2c1: i2c1 {
fsl,pins = <
MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd
MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd
>;
};
pinctrl_i2c2: i2c2 {
fsl,pins = <
MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd
MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd
>;
};
pinctrl_i2c3: i2c3 {
fsl,pins = <
MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd
MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd
>;
};
pinctrl_leds: leds {
fsl,pins = <
MX50_PAD_PWM1__GPIO6_24 0x0
>;
};
pinctrl_sd1: sd1 {
fsl,pins = <
MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4
MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4
MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4
MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4
MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4
MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4
MX50_PAD_SD2_CD__GPIO5_17 0x0
>;
};
pinctrl_sd2: sd2 {
fsl,pins = <
MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4
MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4
MX50_PAD_SD2_D0__ESDHC2_DAT0 0x1d4
MX50_PAD_SD2_D1__ESDHC2_DAT1 0x1d4
MX50_PAD_SD2_D2__ESDHC2_DAT2 0x1d4
MX50_PAD_SD2_D3__ESDHC2_DAT3 0x1d4
>;
};
pinctrl_sd2_reset: sd2-reset {
fsl,pins = <
MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0
>;
};
pinctrl_sd2_vmmc: sd2-vmmc {
fsl,pins = <
MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0
>;
};
pinctrl_sd3: sd3 {
fsl,pins = <
MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4
MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4
MX50_PAD_SD3_D0__ESDHC3_DAT0 0x1d4
MX50_PAD_SD3_D1__ESDHC3_DAT1 0x1d4
MX50_PAD_SD3_D2__ESDHC3_DAT2 0x1d4
MX50_PAD_SD3_D3__ESDHC3_DAT3 0x1d4
MX50_PAD_SD3_D4__ESDHC3_DAT4 0x1d4
MX50_PAD_SD3_D5__ESDHC3_DAT5 0x1d4
MX50_PAD_SD3_D6__ESDHC3_DAT6 0x1d4
MX50_PAD_SD3_D7__ESDHC3_DAT7 0x1d4
>;
};
pinctrl_uart2: uart2 {
fsl,pins = <
MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4
MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4
>;
};
pinctrl_usbphy: usbphy {
fsl,pins = <
MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0
>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg {
phy_type = "utmi_wide";
dr_mode = "peripheral";
status = "okay";
};
&usbphy0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbphy>;
vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
};

23
arch/arm/boot/dts/imx50.dtsi
View File

@ -26,11 +26,21 @@ aliases {
gpio3 = &gpio4; gpio3 = &gpio4;
gpio4 = &gpio5; gpio4 = &gpio5;
gpio5 = &gpio6; gpio5 = &gpio6;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &esdhc1;
mmc1 = &esdhc2;
mmc2 = &esdhc3;
mmc3 = &esdhc4;
serial0 = &uart1; serial0 = &uart1;
serial1 = &uart2; serial1 = &uart2;
serial2 = &uart3; serial2 = &uart3;
serial3 = &uart4; serial3 = &uart4;
serial4 = &uart5; serial4 = &uart5;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &cspi;
}; };
cpus { cpus {
@ -76,6 +86,14 @@ osc {
}; };
}; };
usbphy0: usbphy-0 {
compatible = "usb-nop-xceiv";
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
clock-names = "main_clk";
#phy-cells = <0>;
status = "okay";
};
soc { soc {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -187,7 +205,8 @@ usbotg: usb@53f80000 {
compatible = "fsl,imx50-usb", "fsl,imx27-usb"; compatible = "fsl,imx50-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>; reg = <0x53f80000 0x0200>;
interrupts = <18>; interrupts = <18>;
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbphy = <&usbphy0>;
status = "disabled"; status = "disabled";
}; };
@ -411,7 +430,7 @@ sdma: sdma@63fb0000 {
reg = <0x63fb0000 0x4000>; reg = <0x63fb0000 0x4000>;
interrupts = <6>; interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>, clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>; <&clks IMX5_CLK_AHB>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin";

38
arch/arm/boot/dts/imx51-zii-rdu1.dts
View File

@ -1,42 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* /*
* Copyright (C) 2017 Zodiac Inflight Innovations * Copyright (C) 2017 Zodiac Inflight Innovations
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/ */
/dts-v1/; /dts-v1/;

2
arch/arm/boot/dts/imx51.dtsi
View File

@ -489,7 +489,7 @@ sdma: sdma@83fb0000 {
reg = <0x83fb0000 0x4000>; reg = <0x83fb0000 0x4000>;
interrupts = <6>; interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>, clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>; <&clks IMX5_CLK_AHB>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";

2
arch/arm/boot/dts/imx53-m53.dtsi
View File

@ -52,7 +52,7 @@ &i2c2 {
clock-frequency = <400000>; clock-frequency = <400000>;
status = "okay"; status = "okay";
stmpe610@41 { touchscreen@41 {
compatible = "st,stmpe610"; compatible = "st,stmpe610";
reg = <0x41>; reg = <0x41>;
id = <0>; id = <0>;

311
arch/arm/boot/dts/imx53-m53menlo.dts Normal file
View File

@ -0,0 +1,311 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include "imx53-m53.dtsi"
/ {
model = "MENLO M53 EMBEDDED DEVICE";
compatible = "menlo,m53menlo", "fsl,imx53";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user1 {
label = "TestLed601";
gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
user2 {
label = "TestLed602";
gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
eth {
label = "EthLedYe";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
linux,default-trigger = "none";
};
};
panel {
compatible = "edt,etm070080dh6";
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};
reg_usbh1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2>;
status = "okay";
};
&clks {
assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>,
<&clks IMX5_CLK_CKO1_PODF>,
<&clks IMX5_CLK_CKO1>;
assigned-clock-parents = <&clks IMX5_CLK_AHB>;
assigned-clock-rates = <133333334>, <33333334>, <33333334>;
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
touchscreen@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06>;
interrupt-parent = <&gpio6>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
};
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
dac@60 {
compatible = "microchip,mcp4725";
reg = <0x60>;
};
};
&i2c2 {
touchscreen@41 {
status = "disabled";
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx53-m53evk {
hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
MX53_PAD_EIM_EB3__GPIO2_31 0x1d5
MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5
MX53_PAD_GPIO_19__CCM_CLKO 0x1d5
MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5
MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5
MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5
MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5
MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5
MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5
MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5
MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5
MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5
MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5
MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4
MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4
>;
};
pinctrl_display_gpio: display-gpiogrp {
fsl,pins = <
MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */
MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */
>;
};
pinctrl_edt_ft5x06: edt-ft5x06grp {
fsl,pins = <
MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */
MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */
MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4
MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4
>;
};
pinctrl_lvds0: lvds0grp {
/* LVDS pins only have pin mux configuration */
fsl,pins = <
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
>;
};
pinctrl_usb: usbgrp {
fsl,pins = <
MX53_PAD_GPIO_2__GPIO1_2 0x1d5
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5
>;
};
};
};
&ldb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds0>;
status = "okay";
lvds0: lvds-channel@0 {
reg = <0>;
fsl,data-mapping = "spwg";
fsl,data-width = <18>;
status = "okay";
port@2 {
reg = <2>;
lvds0_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb>;
vbus-supply = <&reg_usbh1_vbus>;
phy_type = "utmi";
dr_mode = "peripheral";
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};

2
arch/arm/boot/dts/imx53.dtsi
View File

@ -702,7 +702,7 @@ sdma: sdma@63fb0000 {
reg = <0x63fb0000 0x4000>; reg = <0x63fb0000 0x4000>;
interrupts = <6>; interrupts = <6>;
clocks = <&clks IMX5_CLK_SDMA_GATE>, clocks = <&clks IMX5_CLK_SDMA_GATE>,
<&clks IMX5_CLK_SDMA_GATE>; <&clks IMX5_CLK_AHB>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";

4
arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi
View File

@ -247,9 +247,9 @@ wm8962: audio-codec@1a {
gpio-cfg = < gpio-cfg = <
0x0000 /* 0:Default */ 0x0000 /* 0:Default */
0x0000 /* 1:Default */ 0x0000 /* 1:Default */
0x0013 /* 2:FN_DMICCLK */ 0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */ 0x0000 /* 3:Default */
0x8014 /* 4:FN_DMICCDAT */ 0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */ 0x0000 /* 5:Default */
>; >;
}; };

381
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts Normal file
View File

@ -0,0 +1,381 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2016 Eckelmann AG.
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6dl.dtsi"
/ {
model = "Eckelmann CI 4X10 Board";
compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
chosen {
stdout-path = &uart3;
};
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x40000000>;
};
rmii_clk: clock-rmii {
/* This clock is provided by the phy (KSZ8091RNB) */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
siox {
compatible = "eckelmann,siox-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_siox>;
din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>;
status = "okay";
flash@0 {
compatible = "everspin,mr25h256";
reg = <0>;
spi-max-frequency = <15000000>;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
status = "okay";
tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <10000000>;
};
};
&gpio2 {
gpio-line-names = "buzzer", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "in2",
"prio2", "prio1", "aux", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio6 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "in1",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
temperature-sensor@49 {
compatible = "ad,ad7414";
reg = <0x49>;
};
rtc@51 {
compatible = "nxp,pcf2127";
reg = <0x51>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hog {
fsl,pins = <
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */
MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0
MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0
MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0
MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098
MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098
MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098
MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0
MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0
MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0
MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0
MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020
MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
/* without SION i2c doesn't detect bus busy */
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018
>;
};
pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
fsl,pins = <
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0
>;
};
pinctrl_siox: sioxgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */
MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */
>;
};
pinctrl_uart1_dte: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010
MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010
MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010
MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */
MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */
>;
};
pinctrl_uart2_dte: uart2grp {
fsl,pins = <
MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010
MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010
MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010
MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */
>;
};
pinctrl_uart3_dce: uart3grp {
fsl,pins = <
MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010
MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010
>;
};
pinctrl_uart4_dce: uart4grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010
MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010
>;
};
pinctrl_uart5_dce: uart5grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010
MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010
MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059
>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_dte>;
uart-has-rtscts;
fsl,dte-mode;
dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_dte>;
uart-has-rtscts;
fsl,dte-mode;
dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_dce>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_dce>;
rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5_dce>;
rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
non-removable;
status = "okay";
};

15
arch/arm/boot/dts/imx6dl-sabreauto.dts
View File

@ -11,3 +11,18 @@ / {
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
}; };
&cpu0 {
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 1150000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1200000
792000 1175000
396000 1175000
>;
};

105
arch/arm/boot/dts/imx6q-gw54xx.dts
View File

@ -12,10 +12,30 @@
/dts-v1/; /dts-v1/;
#include "imx6q.dtsi" #include "imx6q.dtsi"
#include "imx6qdl-gw54xx.dtsi" #include "imx6qdl-gw54xx.dtsi"
#include <dt-bindings/media/tda1997x.h>
/ { / {
model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
simple-audio-card,dai-link@0 {
format = "i2s";
cpu {
sound-dai = <&ssi2>;
};
codec {
bitclock-master;
frame-master;
sound-dai = <&hdmi_receiver>;
};
};
};
}; };
&i2c3 { &i2c3 {
@ -35,6 +55,61 @@ adv7180_to_ipu2_csi1_mux: endpoint {
}; };
}; };
}; };
hdmi_receiver: hdmi-receiver@48 {
compatible = "nxp,tda19971";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tda1997x>;
reg = <0x48>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
DOVDD-supply = <&reg_3p3v>;
AVDD-supply = <&sw4_reg>;
DVDD-supply = <&sw4_reg>;
#sound-dai-cells = <0>;
nxp,audout-format = "i2s";
nxp,audout-layout = <0>;
nxp,audout-width = <16>;
nxp,audout-mclk-fs = <128>;
/*
* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
* and Y[11:4] across 16bits in the same cycle
* which we map to VP[15:08]<->CSI_DATA[19:12]
*/
nxp,vidout-portcfg =
/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
port {
tda1997x_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
data-active = <1>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <16>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
bus-width = <16>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
}; };
&ipu2_csi1_from_ipu2_csi1_mux { &ipu2_csi1_from_ipu2_csi1_mux {
@ -63,6 +138,30 @@ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x4001b0b0
>; >;
}; };
pinctrl_ipu1_csi0: ipu1_csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_ipu2_csi1: ipu2_csi1grp { pinctrl_ipu2_csi1: ipu2_csi1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0
@ -78,4 +177,10 @@ MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b0
MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0
>; >;
}; };
pinctrl_tda1997x: tda1997xgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
>;
};
}; };

4
arch/arm/boot/dts/imx6q-logicpd.dts
View File

@ -21,6 +21,8 @@ backlight: backlight-lvds {
panel-lvds0 { panel-lvds0 {
compatible = "okaya,rs800480t-7x0gp"; compatible = "okaya,rs800480t-7x0gp";
power-supply = <&reg_lcd_reset>;
backlight = <&backlight>;
port { port {
panel_in_lvds0: endpoint { panel_in_lvds0: endpoint {
@ -38,7 +40,6 @@ reg_lcd: regulator-lcd {
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
regulator-always-on;
vin-supply = <&reg_3v3>; vin-supply = <&reg_3v3>;
startup-delay-us = <500000>; startup-delay-us = <500000>;
}; };
@ -52,7 +53,6 @@ reg_lcd_reset: regulator-lcd-reset {
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high; enable-active-high;
regulator-always-on;
vin-supply = <&reg_lcd>; vin-supply = <&reg_lcd>;
}; };
}; };

38
arch/arm/boot/dts/imx6q-zii-rdu2.dts
View File

@ -1,42 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* /*
* Copyright (C) 2016-2017 Zodiac Inflight Innovations * Copyright (C) 2016-2017 Zodiac Inflight Innovations
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/ */
/dts-v1/; /dts-v1/;

29
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View File

@ -10,6 +10,7 @@
*/ */
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ { / {
/* these are used by bootloader for disabling nodes */ /* these are used by bootloader for disabling nodes */
@ -115,12 +116,12 @@ reg_usb_otg_vbus: regulator@3 {
}; };
}; };
sound { sound-analog {
compatible = "fsl,imx6q-ventana-sgtl5000", compatible = "fsl,imx6q-ventana-sgtl5000",
"fsl,imx-audio-sgtl5000"; "fsl,imx-audio-sgtl5000";
model = "sgtl5000-audio"; model = "sgtl5000-audio";
ssi-controller = <&ssi1>; ssi-controller = <&ssi1>;
audio-codec = <&codec>; audio-codec = <&sgtl5000>;
audio-routing = audio-routing =
"MIC_IN", "Mic Jack", "MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias", "Mic Jack", "Mic Bias",
@ -134,6 +135,25 @@ &audmux {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
status = "okay"; status = "okay";
ssi2 {
fsl,audmux-port = <1>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
IMX_AUDMUX_V2_PTCR_SYN)
IMX_AUDMUX_V2_PDCR_RXDSEL(4)
>;
};
aud5 {
fsl,audmux-port = <4>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
};
}; };
&can1 { &can1 {
@ -332,7 +352,7 @@ &i2c3 {
pinctrl-0 = <&pinctrl_i2c3>; pinctrl-0 = <&pinctrl_i2c3>;
status = "okay"; status = "okay";
codec: sgtl5000@a { sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000"; compatible = "fsl,sgtl5000";
reg = <0x0a>; reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>; clocks = <&clks IMX6QDL_CLK_CKO>;
@ -476,6 +496,9 @@ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
>; >;
}; };

138
arch/arm/boot/dts/imx6qdl-gw551x.dtsi
View File

@ -46,6 +46,8 @@
*/ */
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/tda1997x.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>
/ { / {
/* these are used by bootloader for disabling nodes */ /* these are used by bootloader for disabling nodes */
@ -99,6 +101,50 @@ reg_usb_otg_vbus: regulator-usb-otg-vbus {
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
}; };
sound-digital {
compatible = "simple-audio-card";
simple-audio-card,name = "tda1997x-audio";
simple-audio-card,dai-link@0 {
format = "i2s";
cpu {
sound-dai = <&ssi2>;
};
codec {
bitclock-master;
frame-master;
sound-dai = <&hdmi_receiver>;
};
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
status = "okay";
ssi1 {
fsl,audmux-port = <0>;
fsl,port-config = <
(IMX_AUDMUX_V2_PTCR_TFSDIR |
IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
IMX_AUDMUX_V2_PTCR_TCLKDIR |
IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
IMX_AUDMUX_V2_PTCR_SYN)
IMX_AUDMUX_V2_PDCR_RXDSEL(4)
>;
};
aud5 {
fsl,audmux-port = <4>;
fsl,port-config = <
IMX_AUDMUX_V2_PTCR_SYN
IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
};
}; };
&can1 { &can1 {
@ -264,6 +310,60 @@ gpio_exp: pca9555@24 {
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
hdmi_receiver: hdmi-receiver@48 {
compatible = "nxp,tda19971";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tda1997x>;
reg = <0x48>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
DOVDD-supply = <&reg_3p3>;
AVDD-supply = <&reg_1p8b>;
DVDD-supply = <&reg_1p8a>;
#sound-dai-cells = <0>;
nxp,audout-format = "i2s";
nxp,audout-layout = <0>;
nxp,audout-width = <16>;
nxp,audout-mclk-fs = <128>;
/*
* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
* and Y[11:4] across 16bits in the same cycle
* which we map to VP[15:08]<->CSI_DATA[19:12]
*/
nxp,vidout-portcfg =
/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
port {
tda1997x_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
data-active = <1>;
};
};
};
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <16>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
bus-width = <16>;
};
&ipu1_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu1_csi0>;
}; };
&pcie { &pcie {
@ -321,6 +421,14 @@ &wdog1 {
}; };
&iomuxc { &iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0
MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0
>;
};
pinctrl_flexcan1: flexcan1grp { pinctrl_flexcan1: flexcan1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
@ -376,6 +484,30 @@ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>; >;
}; };
pinctrl_ipu1_csi0: ipu1_csi0grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
>;
};
pinctrl_pcie: pciegrp { pinctrl_pcie: pciegrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
@ -400,6 +532,12 @@ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
>; >;
}; };
pinctrl_tda1997x: tda1997xgrp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
>;
};
pinctrl_uart2: uart2grp { pinctrl_uart2: uart2grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1

2
arch/arm/boot/dts/imx6qdl-gw5903.dtsi
View File

@ -311,7 +311,7 @@ &i2c3 {
tlv320aic3105: codec@18 { tlv320aic3105: codec@18 {
compatible = "ti,tlv320aic3x"; compatible = "ti,tlv320aic3x";
reg = <0x18>; reg = <0x18>;
gpio-reset = <&gpio5 17 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
clocks = <&clks IMX6QDL_CLK_CKO>; clocks = <&clks IMX6QDL_CLK_CKO>;
ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */
/* Regulators */ /* Regulators */

4
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View File

@ -79,7 +79,7 @@ &ecspi3 {
status = "okay"; status = "okay";
cs-gpios = <&gpio4 24 0>; cs-gpios = <&gpio4 24 0>;
flash@0 { som_flash: flash@0 {
compatible = "m25p80", "jedec,spi-nor"; compatible = "m25p80", "jedec,spi-nor";
spi-max-frequency = <20000000>; spi-max-frequency = <20000000>;
reg = <0>; reg = <0>;
@ -121,7 +121,7 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
status = "okay"; status = "okay";
eeprom@50 { som_eeprom: eeprom@50 {
compatible = "atmel,24c32"; compatible = "atmel,24c32";
reg = <0x50>; reg = <0x50>;
}; };

2
arch/arm/boot/dts/imx6qdl-var-dart.dtsi
View File

@ -183,7 +183,7 @@ tlv320aic3106: codec@1b {
IOVDD-supply = <&reg_3p3v>; IOVDD-supply = <&reg_3p3v>;
DVDD-supply = <&reg_3p3v>; DVDD-supply = <&reg_3p3v>;
ai3x-ocmv = <0>; ai3x-ocmv = <0>;
gpio-reset = <&gpio5 5 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
}; };
}; };

50
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
View File

@ -1,42 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* /*
* Copyright (C) 2016-2017 Zodiac Inflight Innovations * Copyright (C) 2016-2017 Zodiac Inflight Innovations
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/ */
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
@ -210,6 +174,7 @@ sound2_codec: simple-audio-card,codec {
panel { panel {
power-supply = <&reg_3p3v_display>; power-supply = <&reg_3p3v_display>;
backlight = <&sp_backlight>;
status = "disabled"; status = "disabled";
port { port {
@ -327,7 +292,7 @@ watchdog {
compatible = "zii,rave-sp-watchdog"; compatible = "zii,rave-sp-watchdog";
}; };
backlight { sp_backlight: backlight {
compatible = "zii,rave-sp-backlight"; compatible = "zii,rave-sp-backlight";
}; };
@ -384,7 +349,7 @@ codec2: codec@18 {
AVDD-supply = <&reg_3p3v>; AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>; IOVDD-supply = <&reg_3p3v>;
DVDD-supply = <&vgen4_reg>; DVDD-supply = <&vgen4_reg>;
gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
}; };
accel@1c { accel@1c {
@ -528,6 +493,11 @@ vgen6_reg: vgen6 {
}; };
}; };
watchdog@38 {
compatible = "zii,rave-wdt";
reg = <0x38>;
};
temp-sense@48 { temp-sense@48 {
compatible = "national,lm75"; compatible = "national,lm75";
reg = <0x48>; reg = <0x48>;
@ -572,7 +542,7 @@ codec1: codec@18 {
AVDD-supply = <&reg_3p3v>; AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>; IOVDD-supply = <&reg_3p3v>;
DVDD-supply = <&vgen4_reg>; DVDD-supply = <&vgen4_reg>;
gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
}; };
touchscreen@20 { touchscreen@20 {

18
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -4,6 +4,7 @@
// Copyright 2011 Linaro Ltd. // Copyright 2011 Linaro Ltd.
#include <dt-bindings/clock/imx6qdl-clock.h> #include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
/ { / {
@ -279,6 +280,7 @@ pcie: pcie@1ffc000 {
ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>; num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi"; interrupt-names = "msi";
#interrupt-cells = <1>; #interrupt-cells = <1>;
@ -833,6 +835,14 @@ snvs_poweroff: snvs-poweroff {
status = "disabled"; status = "disabled";
}; };
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
};
snvs_lpgpr: snvs-lpgpr { snvs_lpgpr: snvs-lpgpr {
compatible = "fsl,imx6q-snvs-lpgpr"; compatible = "fsl,imx6q-snvs-lpgpr";
}; };
@ -918,7 +928,7 @@ sdma: sdma@20ec000 {
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>; reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SDMA>, clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_SDMA>; <&clks IMX6QDL_CLK_SDMA>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
@ -1129,14 +1139,16 @@ romcp@21ac000 {
reg = <0x021ac000 0x4000>; reg = <0x021ac000 0x4000>;
}; };
mmdc0: mmdc@21b0000 { /* MMDC0 */ mmdc0: memory-controller@21b0000 { /* MMDC0 */
compatible = "fsl,imx6q-mmdc"; compatible = "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>; reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;
}; };
mmdc1: mmdc@21b4000 { /* MMDC1 */ mmdc1: memory-controller@21b4000 { /* MMDC1 */
compatible = "fsl,imx6q-mmdc";
reg = <0x021b4000 0x4000>; reg = <0x021b4000 0x4000>;
status = "disabled";
}; };
weim: weim@21b8000 { weim: weim@21b8000 {

38
arch/arm/boot/dts/imx6qp-zii-rdu2.dts
View File

@ -1,42 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* /*
* Copyright (C) 2016-2017 Zodiac Inflight Innovations * Copyright (C) 2016-2017 Zodiac Inflight Innovations
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/ */
/dts-v1/; /dts-v1/;

11
arch/arm/boot/dts/imx6sl.dtsi
View File

@ -23,6 +23,13 @@ aliases {
gpio2 = &gpio3; gpio2 = &gpio3;
gpio3 = &gpio4; gpio3 = &gpio4;
gpio4 = &gpio5; gpio4 = &gpio5;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
mmc3 = &usdhc4;
serial0 = &uart1; serial0 = &uart1;
serial1 = &uart2; serial1 = &uart2;
serial2 = &uart3; serial2 = &uart3;
@ -741,7 +748,7 @@ sdma: sdma@20ec000 {
reg = <0x020ec000 0x4000>; reg = <0x020ec000 0x4000>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_SDMA>, clocks = <&clks IMX6SL_CLK_SDMA>,
<&clks IMX6SL_CLK_SDMA>; <&clks IMX6SL_CLK_AHB>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
/* imx6sl reuses imx6q sdma firmware */ /* imx6sl reuses imx6q sdma firmware */
@ -922,7 +929,7 @@ i2c3: i2c@21a8000 {
status = "disabled"; status = "disabled";
}; };
mmdc: mmdc@21b0000 { memory-controller@21b0000 {
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>; reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;

3
arch/arm/boot/dts/imx6sll.dtsi
View File

@ -64,6 +64,7 @@ cpu0: cpu@0 {
198000 1175000 198000 1175000
>; >;
clock-latency = <61036>; /* two CLK32 periods */ clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
clocks = <&clks IMX6SLL_CLK_ARM>, clocks = <&clks IMX6SLL_CLK_ARM>,
<&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_PFD2>,
<&clks IMX6SLL_CLK_STEP>, <&clks IMX6SLL_CLK_STEP>,
@ -621,7 +622,7 @@ sdma: dma-controller@20ec000 {
compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>; reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_SDMA>, clocks = <&clks IMX6SLL_CLK_IPG>,
<&clks IMX6SLL_CLK_SDMA>; <&clks IMX6SLL_CLK_SDMA>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;

4
arch/arm/boot/dts/imx6sx.dtsi
View File

@ -820,7 +820,7 @@ sdma: sdma@20ec000 {
compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
reg = <0x020ec000 0x4000>; reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_SDMA>, clocks = <&clks IMX6SX_CLK_IPG>,
<&clks IMX6SX_CLK_SDMA>; <&clks IMX6SX_CLK_SDMA>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
@ -1017,7 +1017,7 @@ i2c3: i2c@21a8000 {
status = "disabled"; status = "disabled";
}; };
mmdc: mmdc@21b0000 { memory-controller@21b0000 {
compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>; reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;

4
arch/arm/boot/dts/imx6ul.dtsi
View File

@ -708,7 +708,7 @@ sdma: sdma@20ec000 {
"fsl,imx35-sdma"; "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>; reg = <0x020ec000 0x4000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_SDMA>, clocks = <&clks IMX6UL_CLK_IPG>,
<&clks IMX6UL_CLK_SDMA>; <&clks IMX6UL_CLK_SDMA>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
@ -914,7 +914,7 @@ i2c3: i2c@21a8000 {
status = "disabled"; status = "disabled";
}; };
mmdc: mmdc@21b0000 { memory-controller@21b0000 {
compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>; reg = <0x021b0000 0x4000>;
clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;

550
arch/arm/boot/dts/imx7-mba7.dtsi Normal file
View File

@ -0,0 +1,550 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Device Tree Include file for TQ Systems MBa7 carrier board.
*
* Copyright (C) 2016 TQ Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*
* Note: This file does not include nodes for all peripheral devices.
* As device driver coverage increases additional nodes can be added.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
beeper {
compatible = "gpio-beeper";
gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>;
};
chosen {
stdout-path = &uart6;
};
gpio_buttons: gpio-keys {
compatible = "gpio-keys";
button-0 {
/* #SWITCH_A */
label = "S11";
linux,code = <KEY_1>;
gpios = <&pca9555 13 GPIO_ACTIVE_LOW>;
};
button-1 {
/* #SWITCH_B */
label = "S12";
linux,code = <KEY_2>;
gpios = <&pca9555 14 GPIO_ACTIVE_LOW>;
};
button-2 {
/* #SWITCH_C */
label = "S13";
linux,code = <KEY_3>;
gpios = <&pca9555 15 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
led1 {
label = "led1";
gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led2 {
label = "led2";
gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-fixed";
regulator-name = "VCC3V3_SD1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_fec1_pwdn: regulator-fec1-pwdn {
compatible = "regulator-fixed";
regulator-name = "PWDN_FEC1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_fec2_pwdn: regulator-fec2-pwdn {
compatible = "regulator-fixed";
regulator-name = "PWDN_FEC2";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "VBUS_USBOTG1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "VBUS_USBOTG2";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_mpcie_1v5: regulator-mpcie-1v5 {
compatible = "regulator-fixed";
regulator-name = "VCC1V5_MPCIE";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_mpcie_3v3: regulator-mpcie-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3_MPCIE";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_mba_12v0: regulator-mba-12v0 {
compatible = "regulator-fixed";
regulator-name = "VCC12V0_MBA7";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_lvds_transmitter: regulator-lvds-transmitter {
compatible = "regulator-fixed";
regulator-name = "#SHTDN_LVDS";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC1V8_REF";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
vin-supply = <&sw2_reg>;
};
reg_audio_3v3: regulator-audio-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC3V3_AUDIO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&adc2 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
num-chipselects = <3>;
cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>,
<&gpio4 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
num-chipselects = <1>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-delay = <1>;
phy-supply = <&reg_fec1_pwdn>;
phy-handle = <&ethphy1_0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
/* LED1: Link/Activity, LED2: Error */
ti,led-function = <0x0db0>;
/* Active low, LED1 and LED2 driven by phy */
ti,led-ctrl = <0x1001>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&i2c1 {
lm75: temperature-sensor@49 {
compatible = "national,lm75";
reg = <0x49>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
tlv320aic32x4: audio-codec@18 {
compatible = "ti,tlv320aic32x4";
reg = <0x18>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
clock-names = "mclk";
ldoin-supply = <&reg_audio_3v3>;
iov-supply = <&reg_audio_3v3>;
};
pca9555: gpio-expander@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9555>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio7>;
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_mba7_1>;
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74
MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74
MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74
MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c
MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74
MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74
MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02
MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79
/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070
/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a
MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52
>;
};
pinctrl_hog_mba7_1: hogmba71grp {
fsl,pins = <
/* Limitation: WDOG2_B / WDOG2_RESET not usable */
MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c
MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074
/* #BOOT_EN */
MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078
>;
};
pinctrl_pca9555: pca95550grp {
fsl,pins = <
MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76
MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76
MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e
MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76
MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76
MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e
MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d
MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75
MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75
MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e
MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76
MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76
/* Limitation: RTS is not connected */
MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e
>;
};
pinctrl_usdhc1_gpio: usdhc1grp_gpio {
fsl,pins = <
/* WP */
MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c
/* CD */
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c
/* VSELECT */
MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5e
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x57
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
>;
};
};
&iomuxc_lpsr {
pinctrl_pwm1: pwm1grp {
fsl,pins = <
/* LCD_CONTRAST */
MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50
>;
};
pinctrl_usbotg1: usbotg1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59
>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
status = "okay";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
status = "okay";
};
&uart7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
uart-has-rtscts;
status = "okay";
};
&usbh {
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
vbus-supply = <&reg_usb_otg1_vbus>;
srp-disable;
hnp-disable;
adp-disable;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_sd1_vmmc>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Device Tree Include file for TQ Systems TQMa7x boards with full mounted PCB.
*
* Copyright (C) 2016 TQ Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
/ {
memory@80000000 {
device_type = "memory";
/* 512 MB - default configuration */
reg = <0x80000000 0x20000000>;
};
};
&cpu0 {
arm-supply = <&sw1a_reg>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
pfuze3000: pmic@8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic1>;
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
/* NXP SE97BTP with temperature sensor + eeprom */
se97b: temperature-sensor-eeprom@1e {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1e>;
status = "okay";
};
/* ST M24C64 */
m24c64: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
status = "okay";
};
at24c02: eeprom@56 {
compatible = "atmel,24c02";
reg = <0x56>;
pagesize = <16>;
status = "okay";
};
ds1339: rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078
>;
};
pinctrl_pmic1: pmic1grp {
fsl,pins = <
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x56
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x51
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x51
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
>;
};
};
&iomuxc_lpsr {
pinctrl_wdog1: wdog1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
>;
};
};
&sdma {
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
non-removable;
vmmc-supply = <&vgen4_reg>;
vqmmc-supply = <&sw2_reg>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog1>;
/*
* Errata e10574:
* WDOG reset needs to run with WDOG_RESET_B signal enabled.
* X1-51 (WDOG1#) signal needs carrier board handling to reset
* TQMa7 on X1-22 (RESET_IN#).
*/
fsl,ext-reset-output;
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board.
*
* Copyright (C) 2016 TQ Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
/dts-v1/;
#include "imx7d-tqma7.dtsi"
#include "imx7-mba7.dtsi"
/ {
model = "TQ Systems TQMa7D board on MBa7 carrier board";
compatible = "tq,imx7d-mba7", "fsl,imx7d";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-delay = <1>;
phy-supply = <&reg_fec2_pwdn>;
phy-handle = <&ethphy2_0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy2_0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
/* LED1: Link/Activity, LED2: error */
ti,led-function = <0x0db0>;
/* active low, LED1/2 driven by phy */
ti,led-ctrl = <0x1001>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_mba7_1>;
pinctrl_enet2: enet2grp {
fsl,pins = <
MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02
MX7D_PAD_SD2_WP__ENET2_MDC 0x00
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79
/* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */
MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070
/* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */
MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
/* #pcie_wake */
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70
/* #pcie_rst */
MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70
/* #pcie_dis */
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70
>;
};
};
&iomuxc_lpsr {
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59
>;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
/* 1.5V logically from 3.3V */
/* probe deferral not supported */
/* pcie-bus-supply = <&reg_mpcie_1v5>; */
reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
disable-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>;
power-on-gpio = <&gpio2 30 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2>;
vbus-supply = <&reg_usb_otg2_vbus>;
srp-disable;
hnp-disable;
adp-disable;
dr_mode = "host";
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Device Tree Include file for TQ Systems TQMa7D board with NXP i.MX7Dual SoC.
*
* Copyright (C) 2016 TQ Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
#include "imx7d.dtsi"
#include "imx7-tqma7.dtsi"

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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device tree file for ZII's RPU2 board
*
* RPU - Remote Peripheral Unit
*
* Copyright (C) 2019 Zodiac Inflight Innovations
*/
/dts-v1/;
#include <dt-bindings/thermal/thermal.h>
#include "imx7d.dtsi"
/ {
model = "ZII RPU2 Board";
compatible = "zii,imx7d-rpu2", "fsl,imx7d";
chosen {
stdout-path = &uart1;
};
cs2000_ref: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
cs2000_in_dummy: dummy-oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&pinctrl_leds_debug>;
pinctrl-names = "default";
debug {
label = "zii:green:debug1";
gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>,
<&adc2 1>;
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1_stby>;
regulator-name = "can1-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2_stby>;
regulator-name = "can2-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "GEN_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v_main: regulator-5p0v-main {
compatible = "regulator-fixed";
regulator-name = "5V_MAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
sound1 {
compatible = "simple-audio-card";
simple-audio-card,name = "Audio Output 1";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound1_codec>;
simple-audio-card,frame-master = <&sound1_codec>;
simple-audio-card,widgets =
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HPLEFT",
"Headphone Jack", "HPRIGHT",
"LEFTIN", "HPL",
"RIGHTIN", "HPR";
simple-audio-card,aux-devs = <&hpa1>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
sound1_codec: simple-audio-card,codec {
sound-dai = <&codec1>;
clocks = <&cs2000>;
};
};
sound2 {
compatible = "simple-audio-card";
simple-audio-card,name = "Audio Output 2";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound2_codec>;
simple-audio-card,frame-master = <&sound2_codec>;
simple-audio-card,widgets =
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HPLEFT",
"Headphone Jack", "HPRIGHT",
"LEFTIN", "HPL",
"RIGHTIN", "HPR";
simple-audio-card,aux-devs = <&hpa2>;
simple-audio-card,cpu {
sound-dai = <&sai2>;
};
sound2_codec: simple-audio-card,codec {
sound-dai = <&codec2>;
clocks = <&cs2000>;
};
};
sound3 {
compatible = "simple-audio-card";
simple-audio-card,name = "Audio Output 3";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound3_codec>;
simple-audio-card,frame-master = <&sound3_codec>;
simple-audio-card,widgets =
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Headphone Jack", "HPLEFT",
"Headphone Jack", "HPRIGHT",
"LEFTIN", "HPL",
"RIGHTIN", "HPR";
simple-audio-card,aux-devs = <&hpa3>;
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
sound3_codec: simple-audio-card,codec {
sound-dai = <&codec3>;
clocks = <&cs2000>;
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&adc2 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&cpu0 {
arm-supply = <&sw1a_reg>;
};
&clks {
assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <884736000>;
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
switch: switch@0 {
compatible = "marvell,mv88e6085";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_switch>;
reg = <0>;
eeprom-length = <512>;
interrupt-parent = <&gpio1>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "eth_cu_1000_1";
};
port@1 {
reg = <1>;
label = "eth_cu_1000_2";
};
port@2 {
reg = <2>;
label = "pic";
fixed-link {
speed = <100>;
full-duplex;
};
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&fec1>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@6 {
reg = <6>;
label = "gigabit_proc";
ethernet = <&fec2>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
fsl,magic-packet;
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_stby>;
status = "okay";
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>;
gpio-line-names = "", "", "", "", "", "", "", "",
"", "",
"usb_1_en_b",
"usb_2_en_b",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "";
};
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>;
gpio-line-names = "12v_out_en_1",
"12v_out_en_2",
"12v_out_en_3",
"28v_out_en_5",
"28v_out_en_1",
"28v_out_en_2",
"28v_out_en_3",
"28v_out_en_4",
"", "",
"usb_3_en_b",
"usb_4_en_b",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pmic@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
cs2000: clkgen@4e {
compatible = "cirrus,cs2000-cp";
reg = <0x4e>;
#clock-cells = <0>;
clock-names = "clk_in", "ref_clk";
clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
assigned-clocks = <&cs2000>;
assigned-clock-rates = <24000000>;
};
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
};
eeprom@52 {
compatible = "atmel,24c04";
reg = <0x52>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
codec2: codec@18 {
compatible = "ti,tlv320dac3100";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_codec2>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&reg_3p3v>;
SPRVDD-supply = <&reg_3p3v>;
SPLVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
DVDD-supply = <&vgen4_reg>;
gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>;
};
hpa2: amp@60 {
compatible = "ti,tpa6130a2";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpa2>;
reg = <0x60>;
power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
Vdd-supply = <&reg_5p0v_main>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
codec3: codec@18 {
compatible = "ti,tlv320dac3100";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_codec3>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&reg_3p3v>;
SPRVDD-supply = <&reg_3p3v>;
SPLVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
DVDD-supply = <&vgen4_reg>;
gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>;
};
hpa3: amp@60 {
compatible = "ti,tpa6130a2";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpa3>;
reg = <0x60>;
power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>;
Vdd-supply = <&reg_5p0v_main>;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec1: codec@18 {
compatible = "ti,tlv320dac3100";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_codec1>;
reg = <0x18>;
#sound-dai-cells = <0>;
HPVDD-supply = <&reg_3p3v>;
SPRVDD-supply = <&reg_3p3v>;
SPLVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_3p3v>;
IOVDD-supply = <&reg_3p3v>;
DVDD-supply = <&vgen4_reg>;
gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>;
};
hpa1: amp@60 {
compatible = "ti,tpa6130a2";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpa1>;
reg = <0x60>;
power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
Vdd-supply = <&reg_5p0v_main>;
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
<&clks IMX7D_SAI1_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <36864000>;
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>,
<&clks IMX7D_SAI2_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <36864000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
<&clks IMX7D_SAI3_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <36864000>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
rave-sp {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
watchdog {
compatible = "zii,rave-sp-watchdog";
};
eeprom@a3 {
compatible = "zii,rave-sp-eeprom";
reg = <0xa3 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
zii,eeprom-name = "main-eeprom";
};
};
};
&usbotg1 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
no-1-8-v;
no-sdio;
keep-power-in-suspend;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
bus-width = <8>;
no-1-8-v;
non-removable;
no-sdio;
no-sd;
keep-power-in-suspend;
status = "okay";
};
&wdog1 {
status = "disabled";
};
&snvs_rtc {
status = "disabled";
};
&snvs_pwrkey {
status = "disabled";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
MX7D_PAD_SD2_WP__ENET1_MDC 0x3
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59
MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59
>;
};
pinctrl_flexcan1_stby: flexcan1stbygrp {
fsl,pins = <
MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
>;
};
pinctrl_flexcan2_stby: flexcan2stbygrp {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
>;
};
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x00
MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x00
>;
};
pinctrl_gpio2: gpio2grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x00
MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x00
MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x00
MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x03
MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x03
MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x03
MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x03
MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x03
MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x00
MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x00
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f
MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f
MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f
MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f
MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f
>;
};
pinctrl_leds_debug: debuggrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f
MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f
MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f
MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f
MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30
>;
};
pinctrl_tpa1: tpa6130-1grp {
fsl,pins = <
MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x40000038
>;
};
pinctrl_tpa2: tpa6130-2grp {
fsl,pins = <
MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x40000038
>;
};
pinctrl_tpa3: tpa6130-3grp {
fsl,pins = <
MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x40000038
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
>;
};
};
&iomuxc_lpsr {
pinctrl_codec1: dac1grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x40000038
>;
};
pinctrl_codec2: dac2grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x40000038
>;
};
pinctrl_codec3: dac3grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x40000038
>;
};
pinctrl_switch: switchgrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08
>;
};
};

1
arch/arm/boot/dts/imx7d.dtsi
View File

@ -154,6 +154,7 @@ pcie: pcie@33800000 {
ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>; num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi"; interrupt-names = "msi";
#interrupt-cells = <1>; #interrupt-cells = <1>;

18
arch/arm/boot/dts/imx7s-mba7.dts Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Device Tree Source for TQ Systems TQMa7S board on MBa7 carrier board.
*
* Copyright (C) 2016 TQ Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
/dts-v1/;
#include "imx7s-tqma7.dtsi"
#include "imx7-mba7.dtsi"
/ {
model = "TQ Systems TQMa7S board on MBa7 carrier board";
compatible = "tq,imx7s-mba7", "fsl,imx7s";
};

11
arch/arm/boot/dts/imx7s-tqma7.dtsi Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Device Tree Include file for TQ Systems TQMa7S board with NXP i.MX7Solo SoC.
*
* Copyright (C) 2016 TQ Systems GmbH
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
* Copyright (C) 2019 Bruno Thomsen <bruno.thomsen@gmail.com>
*/
#include "imx7s.dtsi"
#include "imx7-tqma7.dtsi"

61
arch/arm/boot/dts/imx7s-warp.dts
View File

@ -55,6 +55,14 @@ reg_bt: regulator-bt {
regulator-always-on; regulator-always-on;
}; };
reg_peri_3p15v: regulator-peri-3p15v {
compatible = "regulator-fixed";
regulator-name = "peri_3p15v_reg";
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
sound { sound {
compatible = "simple-audio-card"; compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000"; simple-audio-card,name = "imx7-sgtl5000";
@ -77,6 +85,10 @@ &clks {
assigned-clock-rates = <884736000>; assigned-clock-rates = <884736000>;
}; };
&csi {
status = "okay";
};
&i2c1 { &i2c1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
@ -121,6 +133,8 @@ sw3a_reg: sw3 {
swbst_reg: swbst { swbst_reg: swbst {
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>; regulator-max-microvolt = <5150000>;
regulator-boot-on;
regulator-always-on;
}; };
snvs_reg: vsnvs { snvs_reg: vsnvs {
@ -178,6 +192,27 @@ &i2c2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>; pinctrl-0 = <&pinctrl_i2c2>;
status = "okay"; status = "okay";
ov2680: camera@36 {
compatible = "ovti,ov2680";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov2680>;
reg = <0x36>;
clocks = <&osc>;
clock-names = "xvclk";
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
DOVDD-supply = <&sw2_reg>;
DVDD-supply = <&sw2_reg>;
AVDD-supply = <&reg_peri_3p15v>;
port {
ov2680_to_mipi: endpoint {
remote-endpoint = <&mipi_from_sensor>;
clock-lanes = <0>;
data-lanes = <1>;
};
};
};
}; };
&i2c3 { &i2c3 {
@ -211,6 +246,22 @@ mpl3115@60 {
}; };
}; };
&mipi_csi {
clock-frequency = <166000000>;
fsl,csis-hs-settle = <3>;
status = "okay";
port@0 {
reg = <0>;
mipi_from_sensor: endpoint {
remote-endpoint = <&ov2680_to_mipi>;
data-lanes = <1>;
};
};
};
&sai1 { &sai1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>; pinctrl-0 = <&pinctrl_sai1>;
@ -277,6 +328,10 @@ &usdhc3 {
status = "okay"; status = "okay";
}; };
&video_mux {
status = "okay";
};
&wdog1 { &wdog1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>; pinctrl-0 = <&pinctrl_wdog>;
@ -331,6 +386,12 @@ MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
>; >;
}; };
pinctrl_ov2680: ov2660grp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
>;
};
pinctrl_sai1: sai1grp { pinctrl_sai1: sai1grp {
fsl,pins = < fsl,pins = <
MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f

98
arch/arm/boot/dts/imx7s.dtsi
View File

@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/imx7-reset.h>
#include "imx7d-pinfunc.h" #include "imx7d-pinfunc.h"
/ { / {
@ -497,8 +498,43 @@ iomuxc: iomuxc@30330000 {
gpr: iomuxc-gpr@30340000 { gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx7d-iomuxc-gpr", compatible = "fsl,imx7d-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon"; "fsl,imx6q-iomuxc-gpr", "syscon",
"simple-mfd";
reg = <0x30340000 0x10000>; reg = <0x30340000 0x10000>;
mux: mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <0>;
mux-reg-masks = <0x14 0x00000010>;
};
video_mux: csi-mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
csi_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_csi_mux>;
};
};
port@2 {
reg = <2>;
csi_mux_to_csi: endpoint {
remote-endpoint = <&csi_from_csi_mux>;
};
};
};
}; };
ocotp: ocotp-ctrl@30350000 { ocotp: ocotp-ctrl@30350000 {
@ -606,7 +642,13 @@ pgc {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pgc_pcie_phy: pgc-power-domain@1 { pgc_mipi_phy: power-domain@0 {
#power-domain-cells = <0>;
reg = <0>;
power-supply = <&reg_1p0d>;
};
pgc_pcie_phy: power-domain@1 {
#power-domain-cells = <0>; #power-domain-cells = <0>;
reg = <1>; reg = <1>;
power-supply = <&reg_1p0d>; power-supply = <&reg_1p0d>;
@ -628,6 +670,7 @@ adc1: adc@30610000 {
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ADC_ROOT_CLK>; clocks = <&clks IMX7D_ADC_ROOT_CLK>;
clock-names = "adc"; clock-names = "adc";
#io-channel-cells = <1>;
status = "disabled"; status = "disabled";
}; };
@ -637,6 +680,7 @@ adc2: adc@30620000 {
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_ADC_ROOT_CLK>; clocks = <&clks IMX7D_ADC_ROOT_CLK>;
clock-names = "adc"; clock-names = "adc";
#io-channel-cells = <1>;
status = "disabled"; status = "disabled";
}; };
@ -696,6 +740,23 @@ pwm4: pwm@30690000 {
status = "disabled"; status = "disabled";
}; };
csi: csi@30710000 {
compatible = "fsl,imx7-csi";
reg = <0x30710000 0x10000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CSI_MCLK_ROOT_CLK>,
<&clks IMX7D_CLK_DUMMY>;
clock-names = "axi", "mclk", "dcic";
status = "disabled";
port {
csi_from_csi_mux: endpoint {
remote-endpoint = <&csi_mux_to_csi>;
};
};
};
lcdif: lcdif@30730000 { lcdif: lcdif@30730000 {
compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
reg = <0x30730000 0x10000>; reg = <0x30730000 0x10000>;
@ -705,6 +766,35 @@ lcdif: lcdif@30730000 {
clock-names = "pix", "axi"; clock-names = "pix", "axi";
status = "disabled"; status = "disabled";
}; };
mipi_csi: mipi-csi@30750000 {
compatible = "fsl,imx7-mipi-csi2";
reg = <0x30750000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_IPG_ROOT_CLK>,
<&clks IMX7D_MIPI_CSI_ROOT_CLK>,
<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
clock-names = "pclk", "wrap", "phy";
power-domains = <&pgc_mipi_phy>;
phy-supply = <&reg_1p0d>;
resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
reset-names = "mrst";
status = "disabled";
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
mipi_vc0_to_csi_mux: endpoint {
remote-endpoint = <&csi_mux_from_mipi_vc0>;
};
};
};
}; };
aips3: aips-bus@30800000 { aips3: aips-bus@30800000 {
@ -1067,8 +1157,8 @@ sdma: sdma@30bd0000 {
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
reg = <0x30bd0000 0x10000>; reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SDMA_CORE_CLK>, clocks = <&clks IMX7D_IPG_ROOT_CLK>,
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; <&clks IMX7D_SDMA_CORE_CLK>;
clock-names = "ipg", "ahb"; clock-names = "ipg", "ahb";
#dma-cells = <3>; #dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";

12
arch/arm/boot/dts/imx7ulp.dtsi
View File

@ -286,6 +286,12 @@ lpuart7: serial@40a70000 {
status = "disabled"; status = "disabled";
}; };
memory-controller@40ab0000 {
compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
reg = <0x40ab0000 0x1000>;
clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
};
iomuxc1: pinctrl@40ac0000 { iomuxc1: pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1"; compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>; reg = <0x40ac0000 0x1000>;
@ -359,5 +365,11 @@ sim: sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon"; compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>; reg = <0x410a3000 0x1000>;
}; };
ocotp: ocotp-ctrl@410a6000 {
compatible = "fsl,imx7ulp-ocotp", "syscon";
reg = <0x410a6000 0x4000>;
clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
};
}; };
}; };

1
arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts
View File

@ -204,7 +204,6 @@ rgmii_phy2: ethernet-phy@2 {
}; };
&qspi { &qspi {
fsl,qspi-has-second-chip;
status = "okay"; status = "okay";
flash: flash@0 { flash: flash@0 {

4
arch/arm/boot/dts/ls1021a-qds.dts
View File

@ -146,6 +146,10 @@ &enet2 {
status = "okay"; status = "okay";
}; };
&esdhc {
status = "okay";
};
&i2c0 { &i2c0 {
status = "okay"; status = "okay";

1
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -186,7 +186,6 @@ qspi: spi@1550000 {
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "qspi_en", "qspi"; clock-names = "qspi_en", "qspi";
clocks = <&clockgen 4 1>, <&clockgen 4 1>; clocks = <&clockgen 4 1>, <&clockgen 4 1>;
big-endian;
status = "disabled"; status = "disabled";
}; };

24
arch/arm/boot/dts/vf610-zii-cfu1.dts
View File

@ -29,35 +29,30 @@ led-debug {
label = "zii:green:debug1"; label = "zii:green:debug1";
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
max-brightness = <1>;
}; };
led-fail { led-fail {
label = "zii:red:fail"; label = "zii:red:fail";
gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
default-state = "off"; default-state = "off";
max-brightness = <1>;
}; };
led-status { led-status {
label = "zii:green:status"; label = "zii:green:status";
gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
default-state = "off"; default-state = "off";
max-brightness = <1>;
}; };
led-debug-a { led-debug-a {
label = "zii:green:debug_a"; label = "zii:green:debug_a";
gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
default-state = "off"; default-state = "off";
max-brightness = <1>;
}; };
led-debug-b { led-debug-b {
label = "zii:green:debug_b"; label = "zii:green:debug_b";
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
default-state = "off"; default-state = "off";
max-brightness = <1>;
}; };
}; };
@ -92,9 +87,14 @@ &dspi1 {
bus-num = <1>; bus-num = <1>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi1>; pinctrl-0 = <&pinctrl_dspi1>;
status = "okay"; /*
* Some CFU1s come with SPI-NOR chip DNPed, so we leave this
* node disabled by default and rely on bootloader to enable
* it when appropriate.
*/
status = "disabled";
m25p128@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "m25p128", "jedec,spi-nor"; compatible = "m25p128", "jedec,spi-nor";
@ -212,7 +212,7 @@ &i2c0 {
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
status = "okay"; status = "okay";
pca9554@22 { io-expander@22 {
compatible = "nxp,pca9554"; compatible = "nxp,pca9554";
reg = <0x22>; reg = <0x22>;
gpio-controller; gpio-controller;
@ -223,19 +223,23 @@ lm75@48 {
reg = <0x48>; reg = <0x48>;
}; };
at24c04@52 { eeprom@52 {
compatible = "atmel,24c04"; compatible = "atmel,24c04";
reg = <0x52>; reg = <0x52>;
label = "nvm"; label = "nvm";
}; };
at24c04@54 { eeprom@54 {
compatible = "atmel,24c04"; compatible = "atmel,24c04";
reg = <0x54>; reg = <0x54>;
label = "nameplate"; label = "nameplate";
}; };
}; };
&snvsrtc {
status = "disabled";
};
&uart0 { &uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>; pinctrl-0 = <&pinctrl_uart0>;

57
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
View File

@ -1,45 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* /*
* Copyright (C) 2015, 2016 Zodiac Inflight Innovations * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
*
* Based on an original 'vf610-twr.dts' which is Copyright 2015,
* Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/ */
/dts-v1/; /dts-v1/;
@ -334,11 +295,11 @@ spi0 {
gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW
&gpio1 8 GPIO_ACTIVE_HIGH>; &gpio1 8 GPIO_ACTIVE_HIGH>;
num-chipselects = <2>; num-chipselects = <2>;
m25p128@0 { flash@0 {
compatible = "m25p128", "jedec,spi-nor"; compatible = "m25p128", "jedec,spi-nor";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -367,7 +328,7 @@ &i2c0 {
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
status = "okay"; status = "okay";
gpio5: pca9554@20 { gpio5: io-expander@20 {
compatible = "nxp,pca9554"; compatible = "nxp,pca9554";
reg = <0x20>; reg = <0x20>;
gpio-controller; gpio-controller;
@ -375,7 +336,7 @@ gpio5: pca9554@20 {
}; };
gpio6: pca9554@22 { gpio6: io-expander@22 {
compatible = "nxp,pca9554"; compatible = "nxp,pca9554";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9554_22>; pinctrl-0 = <&pinctrl_pca9554_22>;
@ -408,7 +369,7 @@ i2c@0 {
#size-cells = <0>; #size-cells = <0>;
reg = <0>; reg = <0>;
sfp1: at24c04@50 { sfp1: eeprom@50 {
compatible = "atmel,24c02"; compatible = "atmel,24c02";
reg = <0x50>; reg = <0x50>;
}; };
@ -419,7 +380,7 @@ i2c@1 {
#size-cells = <0>; #size-cells = <0>;
reg = <1>; reg = <1>;
sfp2: at24c04@50 { sfp2: eeprom@50 {
compatible = "atmel,24c02"; compatible = "atmel,24c02";
reg = <0x50>; reg = <0x50>;
}; };
@ -430,7 +391,7 @@ i2c@2 {
#size-cells = <0>; #size-cells = <0>;
reg = <2>; reg = <2>;
sfp3: at24c04@50 { sfp3: eeprom@50 {
compatible = "atmel,24c02"; compatible = "atmel,24c02";
reg = <0x50>; reg = <0x50>;
}; };
@ -441,7 +402,7 @@ i2c@3 {
#size-cells = <0>; #size-cells = <0>;
reg = <3>; reg = <3>;
sfp4: at24c04@50 { sfp4: eeprom@50 {
compatible = "atmel,24c02"; compatible = "atmel,24c02";
reg = <0x50>; reg = <0x50>;
}; };

49
arch/arm/boot/dts/vf610-zii-dev-rev-c.dts
View File

@ -1,45 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* /*
* Copyright (C) 2015, 2016 Zodiac Inflight Innovations * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
*
* Based on an original 'vf610-twr.dts' which is Copyright 2015,
* Freescale Semiconductor, Inc.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/ */
/dts-v1/; /dts-v1/;
@ -277,7 +238,7 @@ &dspi0 {
status = "okay"; status = "okay";
spi-num-chipselects = <2>; spi-num-chipselects = <2>;
m25p128@0 { flash@0 {
compatible = "m25p128", "jedec,spi-nor"; compatible = "m25p128", "jedec,spi-nor";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
@ -313,7 +274,7 @@ &i2c0 {
* P1 - WE2_CMD * P1 - WE2_CMD
* P2 - WE2_CLK * P2 - WE2_CLK
*/ */
gpio5: pca9557@18 { gpio5: io-expander@18 {
compatible = "nxp,pca9557"; compatible = "nxp,pca9557";
reg = <0x18>; reg = <0x18>;
gpio-controller; gpio-controller;
@ -361,7 +322,7 @@ gpio6: sx1503@20 {
* IO0 - WE1_CLK * IO0 - WE1_CLK
* IO1 - WE1_CMD * IO1 - WE1_CMD
*/ */
gpio7: pca9554@22 { gpio7: io-expander@22 {
compatible = "nxp,pca9554"; compatible = "nxp,pca9554";
reg = <0x22>; reg = <0x22>;
gpio-controller; gpio-controller;
@ -371,7 +332,7 @@ gpio7: pca9554@22 {
}; };
&i2c1 { &i2c1 {
at24mac602@50 { eeprom@50 {
compatible = "atmel,24c02"; compatible = "atmel,24c02";
reg = <0x50>; reg = <0x50>;
read-only; read-only;

6
arch/arm/boot/dts/vf610-zii-dev.dtsi
View File

@ -138,7 +138,7 @@ &i2c0 {
pinctrl-names = "default", "gpio"; pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
pinctrl-1 = <&pinctrl_i2c0_gpio>; pinctrl-1 = <&pinctrl_i2c0_gpio>;
scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
@ -147,12 +147,12 @@ lm75@48 {
reg = <0x48>; reg = <0x48>;
}; };
at24c04@50 { eeprom@50 {
compatible = "atmel,24c04"; compatible = "atmel,24c04";
reg = <0x50>; reg = <0x50>;
}; };
at24c04@52 { eeprom@52 {
compatible = "atmel,24c04"; compatible = "atmel,24c04";
reg = <0x52>; reg = <0x52>;
}; };

14
arch/arm/boot/dts/vf610-zii-scu4-aib.dts
View File

@ -505,14 +505,14 @@ &i2c0 {
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
status = "okay"; status = "okay";
gpio5: pca9554@20 { gpio5: io-expander@20 {
compatible = "nxp,pca9554"; compatible = "nxp,pca9554";
reg = <0x20>; reg = <0x20>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
gpio6: pca9554@22 { gpio6: io-expander@22 {
compatible = "nxp,pca9554"; compatible = "nxp,pca9554";
reg = <0x22>; reg = <0x22>;
gpio-controller; gpio-controller;
@ -524,12 +524,12 @@ lm75@48 {
reg = <0x48>; reg = <0x48>;
}; };
at24c04@50 { eeprom@50 {
compatible = "atmel,24c04"; compatible = "atmel,24c04";
reg = <0x50>; reg = <0x50>;
}; };
at24c04@52 { eeprom@52 {
compatible = "atmel,24c04"; compatible = "atmel,24c04";
reg = <0x52>; reg = <0x52>;
}; };
@ -577,7 +577,7 @@ lm75@4f {
reg = <0x4f>; reg = <0x4f>;
}; };
gpio7: pca9555@23 { gpio7: io-expander@23 {
compatible = "nxp,pca9555"; compatible = "nxp,pca9555";
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
@ -671,6 +671,10 @@ sff9_i2c: i2c@5 {
}; };
}; };
&snvsrtc {
status = "disabled";
};
&uart0 { &uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>; pinctrl-0 = <&pinctrl_uart0>;

359
arch/arm/boot/dts/vf610-zii-spb4.dts Normal file
View File

@ -0,0 +1,359 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device tree file for ZII's SPB4 board
*
* SPB - Seat Power Box
*
* Copyright (C) 2019 Zodiac Inflight Innovations
*/
/dts-v1/;
#include "vf610.dtsi"
/ {
model = "ZII VF610 SPB4 Board";
compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";
chosen {
stdout-path = &uart0;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = <&pinctrl_leds_debug>;
pinctrl-names = "default";
led-debug {
label = "zii:green:debug1";
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_mcu";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc0 {
vref-supply = <&reg_vcc_3v3_mcu>;
status = "okay";
};
&adc1 {
vref-supply = <&reg_vcc_3v3_mcu>;
status = "okay";
};
&dspi1 {
bus-num = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi1>;
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p128", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
&edma0 {
status = "okay";
};
&edma1 {
status = "okay";
};
&esdhc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc0>;
bus-width = <8>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
no-sdio;
no-sd;
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
bus-width = <4>;
no-sdio;
status = "okay";
};
&fec1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
fixed-link {
speed = <100>;
full-duplex;
};
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
switch0: switch0@0 {
compatible = "marvell,mv88e6190";
pinctrl-0 = <&pinctrl_gpio_switch0>;
pinctrl-names = "default";
reg = <0>;
eeprom-length = <65536>;
reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio3>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&fec1>;
fixed-link {
speed = <100>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "eth_cu_1000_1";
};
port@2 {
reg = <2>;
label = "eth_cu_1000_2";
};
port@3 {
reg = <3>;
label = "eth_cu_1000_3";
};
port@4 {
reg = <4>;
label = "eth_cu_1000_4";
};
port@5 {
reg = <5>;
label = "eth_cu_1000_5";
};
port@6 {
reg = <6>;
label = "eth_cu_1000_6";
};
};
};
};
};
&i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
status = "okay";
io-expander@22 {
compatible = "nxp,pca9554";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom@50 {
compatible = "atmel,24c04";
reg = <0x50>;
label = "nameplate";
};
eeprom@52 {
compatible = "atmel,24c04";
reg = <0x52>;
};
};
&snvsrtc {
status = "disabled";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
rave-sp {
compatible = "zii,rave-sp-rdu2";
current-speed = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
watchdog {
compatible = "zii,rave-sp-watchdog";
};
eeprom@a3 {
compatible = "zii,rave-sp-eeprom";
reg = <0xa3 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
zii,eeprom-name = "main-eeprom";
};
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&wdoga5 {
status = "disabled";
};
&iomuxc {
pinctrl_dspi1: dspi1grp {
fsl,pins = <
VF610_PAD_PTD5__DSPI1_CS0 0x1182
VF610_PAD_PTD4__DSPI1_CS1 0x1182
VF610_PAD_PTC6__DSPI1_SIN 0x1181
VF610_PAD_PTC7__DSPI1_SOUT 0x1182
VF610_PAD_PTC8__DSPI1_SCK 0x1182
>;
};
pinctrl_esdhc0: esdhc0grp {
fsl,pins = <
VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
VF610_PAD_PTA6__RMII_CLKIN 0x30d1
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};
pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
fsl,pins = <
VF610_PAD_PTE2__GPIO_107 0x31c2
VF610_PAD_PTB28__GPIO_98 0x219d
>;
};
pinctrl_i2c0: i2c0grp {
fsl,pins = <
VF610_PAD_PTB14__I2C0_SCL 0x37ff
VF610_PAD_PTB15__I2C0_SDA 0x37ff
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
VF610_PAD_PTB16__I2C1_SCL 0x37ff
VF610_PAD_PTB17__I2C1_SDA 0x37ff
>;
};
pinctrl_leds_debug: pinctrl-leds-debug {
fsl,pins = <
VF610_PAD_PTD3__GPIO_82 0x31c2
>;
};
pinctrl_uart0: uart0grp {
fsl,pins = <
VF610_PAD_PTB10__UART0_TX 0x21a2
VF610_PAD_PTB11__UART0_RX 0x21a1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
VF610_PAD_PTB23__UART1_TX 0x21a2
VF610_PAD_PTB24__UART1_RX 0x21a1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
VF610_PAD_PTD0__UART2_TX 0x21a2
VF610_PAD_PTD1__UART2_RX 0x21a1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
VF610_PAD_PTA30__UART3_TX 0x21a2
VF610_PAD_PTA31__UART3_RX 0x21a1
>;
};
};

5
arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts
View File

@ -37,7 +37,6 @@ led-debug {
label = "zii:green:debug1"; label = "zii:green:debug1";
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
max-brightness = <1>;
}; };
}; };
@ -211,6 +210,10 @@ eeprom@52 {
}; };
}; };
&snvsrtc {
status = "disabled";
};
&uart0 { &uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>; pinctrl-0 = <&pinctrl_uart0>;

17
arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts
View File

@ -37,7 +37,6 @@ led-debug {
label = "zii:green:debug1"; label = "zii:green:debug1";
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
max-brightness = <1>;
}; };
}; };
@ -70,7 +69,7 @@ &dspi1 {
*/ */
status = "disabled"; status = "disabled";
m25p128@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "m25p128", "jedec,spi-nor"; compatible = "m25p128", "jedec,spi-nor";
@ -195,7 +194,7 @@ &i2c0 {
pinctrl-0 = <&pinctrl_i2c0>; pinctrl-0 = <&pinctrl_i2c0>;
status = "okay"; status = "okay";
gpio6: pca9505@22 { gpio6: io-expander@22 {
compatible = "nxp,pca9554"; compatible = "nxp,pca9554";
reg = <0x22>; reg = <0x22>;
gpio-controller; gpio-controller;
@ -207,18 +206,22 @@ lm75@48 {
reg = <0x48>; reg = <0x48>;
}; };
at24c04@50 { eeprom@50 {
compatible = "atmel,24c04"; compatible = "atmel,24c04";
reg = <0x50>; reg = <0x50>;
label = "nameplate"; label = "nameplate";
}; };
at24c04@52 { eeprom@52 {
compatible = "atmel,24c04"; compatible = "atmel,24c04";
reg = <0x52>; reg = <0x52>;
}; };
}; };
&snvsrtc {
status = "disabled";
};
&uart0 { &uart0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>; pinctrl-0 = <&pinctrl_uart0>;
@ -250,6 +253,10 @@ eeprom@a3 {
}; };
}; };
&wdoga5 {
status = "disabled";
};
&iomuxc { &iomuxc {
pinctrl_dspi1: dspi1grp { pinctrl_dspi1: dspi1grp {
fsl,pins = < fsl,pins = <