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clk: mmp2: Add HSIC clocks
There are two USB HSIC controllers on MMP2 and MMP3. Link: https://lore.kernel.org/r/20191220065314.237624-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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@ -53,6 +53,8 @@
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#define APMU_DISP1 0x110
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#define APMU_CCIC0 0x50
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#define APMU_CCIC1 0xf4
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#define APMU_USBHSIC0 0xf8
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#define APMU_USBHSIC1 0xfc
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#define MPMU_UART_PLL 0x14
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struct mmp2_clk_unit {
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@ -194,6 +196,8 @@ static struct mmp_clk_mix_config sdh_mix_config = {
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};
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static DEFINE_SPINLOCK(usb_lock);
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static DEFINE_SPINLOCK(usbhsic0_lock);
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static DEFINE_SPINLOCK(usbhsic1_lock);
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static DEFINE_SPINLOCK(disp0_lock);
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static DEFINE_SPINLOCK(disp1_lock);
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@ -224,6 +228,8 @@ static struct mmp_param_div_clk apmu_div_clks[] = {
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static struct mmp_param_gate_clk apmu_gate_clks[] = {
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{MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
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{MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_lock},
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{MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_lock},
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/* The gate clocks has mux parent. */
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{MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
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{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
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