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ACPI / CPPC: replace writeX/readX to PCC with relaxed version 

We do not have a strict read/write order requirement while accessing
PCC subspace. The only requirement is all access should be committed
before triggering the PCC doorbell to transfer the ownership of PCC
to the platform and this requirement is enforced by the PCC driver.

Profiling on a many core system shows improvement of about 1.8us on
average per freq change request(about 10% improvement on average).
Since these operations are executed while holding the pcc_lock,
reducing this time helps the CPPC implementation to scale much
better as the number of cores increases.

Signed-off-by: Prashanth Prakash <pprakash@codeaurora.org>
Acked-by: Ashwin Chaugule <ashwin.chaugule@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Prakash, Prashanth 2016-02-17 13:21:02 -07:00 committed by Rafael J. Wysocki
parent 8b0f578898
commit beee23aebc
1 changed files with 10 additions and 10 deletions
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20
drivers/acpi/cppc_acpi.c
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@ -116,10 +116,10 @@ static int send_pcc_cmd(u16 cmd)
}
/* Write to the shared comm region. */
writew(cmd, &generic_comm_base->command);
writew_relaxed(cmd, &generic_comm_base->command);
/* Flip CMD COMPLETE bit */
writew(0, &generic_comm_base->status);
writew_relaxed(0, &generic_comm_base->status);
/* Ring doorbell */
ret = mbox_send_message(pcc_channel, &cmd);
@ -601,16 +601,16 @@ static int cpc_read(struct cpc_reg *reg, u64 *val)
switch (reg->bit_width) {
case 8:
*val = readb(vaddr);
*val = readb_relaxed(vaddr);
break;
case 16:
*val = readw(vaddr);
*val = readw_relaxed(vaddr);
break;
case 32:
*val = readl(vaddr);
*val = readl_relaxed(vaddr);
break;
case 64:
*val = readq(vaddr);
*val = readq_relaxed(vaddr);
break;
default:
pr_debug("Error: Cannot read %u bit width from PCC\n",
@ -632,16 +632,16 @@ static int cpc_write(struct cpc_reg *reg, u64 val)
switch (reg->bit_width) {
case 8:
writeb(val, vaddr);
writeb_relaxed(val, vaddr);
break;
case 16:
writew(val, vaddr);
writew_relaxed(val, vaddr);
break;
case 32:
writel(val, vaddr);
writel_relaxed(val, vaddr);
break;
case 64:
writeq(val, vaddr);
writeq_relaxed(val, vaddr);
break;
default:
pr_debug("Error: Cannot write %u bit width to PCC\n",