mirror of https://gitee.com/openkylin/linux.git
ARM: dts: imx6ul-14x14-evk: Add audio support
imx6ul-14x14-evk has a wm8960 codec connected via SAI2 port. Add support for it. Thanks to Petr Kulhavy <brain@jikos.cz> for the hint on initializing the PLL4 frequency to get a correct MCLK. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -36,6 +36,45 @@ reg_sd1_vmmc: sd1_regulator {
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enable-active-high;
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};
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "mx6ul-wm8960";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-master = <&dailink_master>;
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simple-audio-card,frame-master = <&dailink_master>;
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simple-audio-card,widgets =
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"Microphone", "Mic Jack",
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"Line", "Line In",
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"Line", "Line Out",
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"Speaker", "Speaker",
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"Headphone", "Headphone Jack";
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simple-audio-card,routing =
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"Headphone Jack", "HP_L",
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"Headphone Jack", "HP_R",
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"Speaker", "SPK_LP",
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"Speaker", "SPK_LN",
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"Speaker", "SPK_RP",
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"Speaker", "SPK_RN",
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"LINPUT1", "Mic Jack",
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"LINPUT3", "Mic Jack",
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"RINPUT1", "Mic Jack",
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"RINPUT2", "Mic Jack";
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simple-audio-card,cpu {
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sound-dai = <&sai2>;
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&codec>;
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clocks = <&clks IMX6UL_CLK_SAI2>;
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};
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};
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&cpu0 {
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@ -43,6 +82,20 @@ &cpu0 {
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soc-supply = <®_soc>;
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};
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&i2c2 {
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clock_frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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codec: wm8960@1a {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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wlf,shared-lrclk;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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@ -86,6 +139,16 @@ flash0: n25q256a@0 {
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};
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};
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&sai2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
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<&clks IMX6UL_CLK_SAI2>;
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assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <0>, <12288000>;
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status = "okay";
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};
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&snvs_poweroff {
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status = "okay";
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};
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@ -272,6 +335,17 @@ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
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MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
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MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
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MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
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MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
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MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
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>;
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};
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pinctrl_pwm1: pwm1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
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