clk: samsung: exynos5250: Correct parent list of audio muxes

According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
This commit is contained in:
Tomasz Figa 2013-10-15 19:41:20 +02:00
parent 256dd646a3
commit bfeb9f274b
1 changed files with 3 additions and 3 deletions

View File

@ -208,19 +208,19 @@ PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m",
"none", "none", "none", "none", "none", "none",
"none" }; "none" };
PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
"sclk_uhostphy", "sclk_hdmiphy", "sclk_uhostphy", "fin_pll",
"mout_mpll_user", "mout_epll", "mout_vpll", "mout_mpll_user", "mout_epll", "mout_vpll",
"mout_cpll", "none", "none", "mout_cpll", "none", "none",
"none", "none", "none", "none", "none", "none",
"none" }; "none" };
PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
"sclk_uhostphy", "sclk_hdmiphy", "sclk_uhostphy", "fin_pll",
"mout_mpll_user", "mout_epll", "mout_vpll", "mout_mpll_user", "mout_epll", "mout_vpll",
"mout_cpll", "none", "none", "mout_cpll", "none", "none",
"none", "none", "none", "none", "none", "none",
"none" }; "none" };
PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy",
"sclk_uhostphy", "sclk_hdmiphy", "sclk_uhostphy", "fin_pll",
"mout_mpll_user", "mout_epll", "mout_vpll", "mout_mpll_user", "mout_epll", "mout_vpll",
"mout_cpll", "none", "none", "mout_cpll", "none", "none",
"none", "none", "none", "none", "none", "none",