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[POWERPC] 85xx: Add next-level-cache property 

Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec.  Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2008-05-30 13:43:43 -05:00
parent acd4b715ec
commit c054065bc1
16 changed files with 32 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/powerpc/boot/dts/ksi8560.dts
View File

@ -40,6 +40,7 @@ PowerPC,8560@0 {
timebase-frequency = <0>; /* From U-boot */
bus-frequency = <0>; /* From U-boot */
clock-frequency = <0>; /* From U-boot */
next-level-cache = <&L2>;
};
};
@ -62,7 +63,7 @@ memory-controller@2000 {
interrupts = <0x12 0x2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; /* 32 bytes */

3
arch/powerpc/boot/dts/mpc8540ads.dts
View File

@ -40,6 +40,7 @@ PowerPC,8540@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};
@ -63,7 +64,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes

3
arch/powerpc/boot/dts/mpc8541cds.dts
View File

@ -40,6 +40,7 @@ PowerPC,8541@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};
@ -63,7 +64,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8541-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes

3
arch/powerpc/boot/dts/mpc8544ds.dts
View File

@ -41,6 +41,7 @@ PowerPC,8544@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -65,7 +66,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8544-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes

3
arch/powerpc/boot/dts/mpc8548cds.dts
View File

@ -45,6 +45,7 @@ PowerPC,8548@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};
@ -68,7 +69,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes

3
arch/powerpc/boot/dts/mpc8555cds.dts
View File

@ -40,6 +40,7 @@ PowerPC,8555@0 {
timebase-frequency = <0>; // 33 MHz, from uboot
bus-frequency = <0>; // 166 MHz
clock-frequency = <0>; // 825 MHz, from uboot
next-level-cache = <&L2>;
};
};
@ -63,7 +64,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8555-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes

2
arch/powerpc/boot/dts/mpc8560ads.dts
View File

@ -64,7 +64,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes

3
arch/powerpc/boot/dts/mpc8568mds.dts
View File

@ -42,6 +42,7 @@ PowerPC,8568@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -70,7 +71,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8568-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes

4
arch/powerpc/boot/dts/mpc8572ds.dts
View File

@ -42,6 +42,7 @@ PowerPC,8572@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
PowerPC,8572@1 {
@ -54,6 +55,7 @@ PowerPC,8572@1 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -84,7 +86,7 @@ memory-controller@6000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,mpc8572-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>; // 32 bytes

3
arch/powerpc/boot/dts/sbc8548.dts
View File

@ -44,6 +44,7 @@ PowerPC,8548@0 {
timebase-frequency = <0>; // From uboot
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -161,7 +162,7 @@ memory-controller@2000 {
interrupts = <0x12 0x2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8548-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; // 32 bytes

3
arch/powerpc/boot/dts/sbc8560.dts
View File

@ -43,6 +43,7 @@ PowerPC,8560@0 {
timebase-frequency = <0>; // From uboot
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -66,7 +67,7 @@ memory-controller@2000 {
interrupts = <0x12 0x2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8560-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <0x20>; // 32 bytes

3
arch/powerpc/boot/dts/stx_gp3_8560.dts
View File

@ -38,6 +38,7 @@ PowerPC,8560@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -62,7 +63,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;

3
arch/powerpc/boot/dts/tqm8540.dts
View File

@ -40,6 +40,7 @@ PowerPC,8540@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -64,7 +65,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;

3
arch/powerpc/boot/dts/tqm8541.dts
View File

@ -39,6 +39,7 @@ PowerPC,8541@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -63,7 +64,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;

3
arch/powerpc/boot/dts/tqm8555.dts
View File

@ -39,6 +39,7 @@ PowerPC,8555@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -63,7 +64,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;

3
arch/powerpc/boot/dts/tqm8560.dts
View File

@ -40,6 +40,7 @@ PowerPC,8560@0 {
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
next-level-cache = <&L2>;
};
};
@ -64,7 +65,7 @@ memory-controller@2000 {
interrupts = <18 2>;
};
l2-cache-controller@20000 {
L2: l2-cache-controller@20000 {
compatible = "fsl,8540-l2-cache-controller";
reg = <0x20000 0x1000>;
cache-line-size = <32>;