mirror of https://gitee.com/openkylin/linux.git
clk: zynqmp: fix check for fractional clock
The firmware sets BIT(13) in clkflag to mark a divider as fractional divider. The clock driver copies the clkflag straight to the flags of the common clock framework. In the common clk framework flags, BIT(13) is defined as CLK_DUTY_CYCLE_PARENT. Add a new field to the zynqmp_clk_divider to specify if a divider is a fractional devider. Set this field based on the clkflag when registering a divider. At the same time, unset BIT(13) from clkflag when copying the flags to the common clk framework flags. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -31,12 +31,14 @@
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* struct zynqmp_clk_divider - adjustable divider clock
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* @hw: handle between common and hardware-specific interfaces
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* @flags: Hardware specific flags
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* @is_frac: The divider is a fractional divider
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* @clk_id: Id of clock
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* @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
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*/
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struct zynqmp_clk_divider {
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struct clk_hw hw;
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u8 flags;
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bool is_frac;
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u32 clk_id;
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u32 div_type;
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};
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@ -123,8 +125,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
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bestdiv = zynqmp_divider_get_val(*prate, rate);
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if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) &&
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(divider->flags & CLK_FRAC))
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if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
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bestdiv = rate % *prate ? 1 : bestdiv;
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*prate = rate * bestdiv;
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@ -202,11 +203,13 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
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init.name = name;
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init.ops = &zynqmp_clk_divider_ops;
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init.flags = nodes->flag;
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/* CLK_FRAC is not defined in the common clk framework */
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init.flags = nodes->flag & ~CLK_FRAC;
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init.parent_names = parents;
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init.num_parents = 1;
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/* struct clk_divider assignments */
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div->is_frac = !!(nodes->flag & CLK_FRAC);
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div->flags = nodes->type_flag;
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div->hw.init = &init;
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div->clk_id = clk_id;
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