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clk: renesas: r8a77995: Simplify PLL3 multiplier/divider 

116/6 can be simplified to 58/3.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Geert Uytterhoeven 2018-10-17 12:00:33 +02:00
parent 6155bfa32c
commit c0f8584f05
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/renesas/r8a77995-cpg-mssr.c
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@ -191,14 +191,14 @@ static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
*--------------------------------------------------------------------
* 0 48 x 1 x250/4 x100/3 x100/3
* 1 48 x 1 x250/4 x100/3 x116/6
* 1 48 x 1 x250/4 x100/3 x58/3
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div */
{ 1, 100, 3, 100, 3, },
{ 1, 100, 3, 116, 6, },
{ 1, 100, 3, 58, 3, },
};
static int __init r8a77995_cpg_mssr_init(struct device *dev)