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clk: tegra: Warn if an enabled PLL is in IDDQ 

A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a
configuration that makes sense, so warn about it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Thierry Reding 2019-06-13 18:12:24 +02:00 committed by Stephen Boyd
parent 2067507012
commit c1139d2083
1 changed files with 5 additions and 1 deletions
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6
drivers/clk/tegra/clk-tegra210.c
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@ -1014,8 +1014,12 @@ static void tegra210_pllre_set_defaults(struct tegra_clk_pll *pllre)
_pll_misc_chk_default(clk_base, pllre->params, 0, val, _pll_misc_chk_default(clk_base, pllre->params, 0, val,
~mask & PLLRE_MISC0_WRITE_MASK); ~mask & PLLRE_MISC0_WRITE_MASK);
/* Enable lock detect */ /* The PLL doesn't work if it's in IDDQ. */
val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]); val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
if (val & PLLRE_MISC0_IDDQ)
pr_warn("unexpected IDDQ bit set for enabled clock\n");
/* Enable lock detect */
val &= ~mask; val &= ~mask;
val |= PLLRE_MISC0_DEFAULT_VALUE & mask; val |= PLLRE_MISC0_DEFAULT_VALUE & mask;
writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]); writel_relaxed(val, clk_base + pllre->params->ext_misc_reg[0]);