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i.MX clock changes for 5.12: 

- Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk
   reparenting.
 - A couple of W=1 build warning fixes from Lee Jones.
 - A series from Liu Ying that adds some SCU clocks support for i.MX8qxp
   DC0/MIPI-LVDS subsystems.
 - A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ,
   and clkout1/2 support for i.MX8MM/MN.
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Merge tag 'clk-imx-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx

Pull i.MX clk driver updates from Shawn Guo:

 - Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk
   reparenting
 - A couple of W=1 build warning fixes from Lee Jones
 - A series from Liu Ying that adds some SCU clocks support for i.MX8qxp
   DC0/MIPI-LVDS subsystems
 - A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ,
   and clkout1/2 support for i.MX8MM/MN

* tag 'clk-imx-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header
  clk: imx8mn: add clkout1/2 support
  clk: imx8mm: add clkout1/2 support
  clk: imx8mq: add PLL monitor output
  clk: imx: clk-imx31: Remove unused static const table 'uart_clks'
  clk: imx6q: demote warning about pre-boot ldb_di_clk reparenting
  clk: imx: clk-imx8qxp: Add some SCU clocks support for MIPI-LVDS subsystems
  clk: imx: clk-imx8qxp: Register DC0 display clocks with imx_clk_scu2()
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 bypass clocks
  clk: imx: clk-imx8qxp: Add SCU clocks support for DC0 PLL clocks
This commit is contained in:
Stephen Boyd 2021-02-04 11:49:12 -08:00
parent 5c8fe583cc de5774d192
commit c148c1bb2a
15 changed files with 125 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-imx/common.h
View File

@ -85,7 +85,6 @@ void imx_anatop_pre_suspend(void);
void imx_anatop_post_resume(void);
int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
void imx6_set_int_mem_clk_lpm(bool enable);
void imx6sl_set_wait_clk(bool enter);
int imx_mmdc_get_ddr_type(void);
int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);

1
arch/arm/mach-imx/cpuidle-imx6sl.c
View File

@ -3,6 +3,7 @@
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*/
#include <linux/clk/imx.h>
#include <linux/cpuidle.h>
#include <linux/module.h>
#include <asm/cpuidle.h>

1
arch/arm/mach-imx/pm-imx6.c
View File

@ -4,6 +4,7 @@
* Copyright 2011 Linaro Ltd.
*/
#include <linux/clk/imx.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>

10
drivers/clk/imx/clk-imx31.c
View File

@ -51,16 +51,6 @@ enum mx31_clks {
static struct clk *clk[clk_max];
static struct clk_onecell_data clk_data;
static struct clk ** const uart_clks[] __initconst = {
&clk[ipg],
&clk[uart1_gate],
&clk[uart2_gate],
&clk[uart3_gate],
&clk[uart4_gate],
&clk[uart5_gate],
NULL
};
static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
{
clk[dummy] = imx_clk_fixed("dummy", 0);

6
drivers/clk/imx/clk-imx6q.c
View File

@ -338,10 +338,10 @@ static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
for (i = 0; i < 2; i++) {
/* Warn if a glitch might have been introduced already */
/* Print a notice if a glitch might have been introduced already */
if (sel[i][0] != 3) {
pr_warn("ccm: ldb_di%d_sel already changed from reset value: %d\n",
i, sel[i][0]);
pr_notice("ccm: possible glitch: ldb_di%d_sel already changed from reset value: %d\n",
i, sel[i][0]);
}
if (sel[i][0] == sel[i][3])

1
drivers/clk/imx/clk-imx6sl.c
View File

@ -6,6 +6,7 @@
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/imx.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>

12
drivers/clk/imx/clk-imx8mm.c
View File

@ -288,6 +288,11 @@ static const char *imx8mm_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "dummy", "
static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", };
static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
static struct clk_hw_onecell_data *clk_hw_data;
static struct clk_hw **hws;
@ -410,6 +415,13 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
hws[IMX8MM_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
hws[IMX8MM_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
hws[IMX8MM_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
hws[IMX8MM_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
hws[IMX8MM_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
hws[IMX8MM_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
hws[IMX8MM_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
hws[IMX8MM_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
np = dev->of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(IS_ERR(base)))

12
drivers/clk/imx/clk-imx8mn.c
View File

@ -281,6 +281,11 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
"video_pll1_out", "osc_32k", };
static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
"dummy", "dummy", "gpu_pll_out", "dummy",
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
static struct clk_hw_onecell_data *clk_hw_data;
static struct clk_hw **hws;
@ -405,6 +410,13 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux("clkout1_sel", base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", base + 0x128, 0, 4);
hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8);
hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux("clkout2_sel", base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels));
hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, 16, 4);
hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24);
np = dev->of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(IS_ERR(base))) {

22
drivers/clk/imx/clk-imx8mq.c
View File

@ -270,6 +270,14 @@ static const char * const imx8mq_clko1_sels[] = {"osc_25m", "sys1_pll_800m", "os
static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_400m", "sys2_pll_166m",
"sys3_pll_out", "audio_pll1_out", "video_pll1_out", "ckil", };
static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy", "dummy", "ckil",
"audio_pll1_out_monitor", "audio_pll2_out_monitor",
"video_pll1_out_monitor", "gpu_pll_out_monitor",
"vpu_pll_out_monitor", "arm_pll_out_monitor",
"sys_pll1_out_monitor", "sys_pll2_out_monitor",
"sys_pll3_out_monitor", "dram_pll_out_monitor",
"video_pll2_out_monitor", };
static struct clk_hw_onecell_data *clk_hw_data;
static struct clk_hw **hws;
@ -399,6 +407,20 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);
hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor", "video_pll1_bypass", base + 0x78, 8, 3);
hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor", "gpu_pll_bypass", base + 0x78, 12, 3);
hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor", "vpu_pll_bypass", base + 0x78, 16, 3);
hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor", "arm_pll_bypass", base + 0x78, 20, 3);
hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor", "sys1_pll_out", base + 0x7c, 0, 3);
hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor", "sys2_pll_out", base + 0x7c, 4, 3);
hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor", "sys3_pll_out", base + 0x7c, 8, 3);
hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor", "dram_pll_out", base + 0x7c, 12, 3);
hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor", "video2_pll_out", base + 0x7c, 16, 3);
hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel", base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels));
hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2", "pllout_monitor_sel", base + 0x74, 4);
np = dev->of_node;
base = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(IS_ERR(base)))

26
drivers/clk/imx/clk-imx8qxp.c
View File

@ -17,6 +17,14 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/firmware/imx/rsrc.h>
static const char *dc0_sels[] = {
"clk_dummy",
"clk_dummy",
"dc0_pll0_clk",
"dc0_pll1_clk",
"dc0_bypass0_clk",
};
static int imx8qxp_clk_probe(struct platform_device *pdev)
{
struct device_node *ccm_node = pdev->dev.of_node;
@ -115,12 +123,26 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
/* Display controller SS */
clks[IMX_DC0_DISP0_CLK] = imx_clk_scu("dc0_disp0_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
clks[IMX_DC0_DISP1_CLK] = imx_clk_scu("dc0_disp1_clk", IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
clks[IMX_DC0_DISP0_CLK] = imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
clks[IMX_DC0_DISP1_CLK] = imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
clks[IMX_DC0_PLL0_CLK] = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
clks[IMX_DC0_PLL1_CLK] = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
clks[IMX_DC0_BYPASS0_CLK] = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_DC0_BYPASS1_CLK] = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
/* MIPI-LVDS SS */
clks[IMX_MIPI0_LVDS_PIXEL_CLK] = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_MIPI0_LVDS_PHY_CLK] = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_PWM0_CLK] = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_MIPI1_LVDS_PIXEL_CLK] = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_MIPI1_LVDS_PHY_CLK] = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
clks[IMX_MIPI1_I2C0_CLK] = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_I2C1_CLK] = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_PWM0_CLK] = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
/* MIPI CSI SS */
clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);

2
include/dt-bindings/clock/imx8-clock.h
View File

@ -64,6 +64,8 @@
#define IMX_DC0_PLL1_CLK 81
#define IMX_DC0_DISP0_CLK 82
#define IMX_DC0_DISP1_CLK 83
#define IMX_DC0_BYPASS0_CLK 84
#define IMX_DC0_BYPASS1_CLK 85
/* MIPI-LVDS SS */
#define IMX_MIPI_IPG_CLK 90

10
include/dt-bindings/clock/imx8mm-clock.h
View File

@ -274,6 +274,14 @@
#define IMX8MM_CLK_A53_CORE 251
#define IMX8MM_CLK_END 252
#define IMX8MM_CLK_CLKOUT1_SEL 252
#define IMX8MM_CLK_CLKOUT1_DIV 253
#define IMX8MM_CLK_CLKOUT1 254
#define IMX8MM_CLK_CLKOUT2_SEL 255
#define IMX8MM_CLK_CLKOUT2_DIV 256
#define IMX8MM_CLK_CLKOUT2 257
#define IMX8MM_CLK_END 258
#endif

9
include/dt-bindings/clock/imx8mn-clock.h
View File

@ -234,6 +234,13 @@
#define IMX8MN_CLK_A53_CORE 214
#define IMX8MN_CLK_END 215
#define IMX8MN_CLK_CLKOUT1_SEL 215
#define IMX8MN_CLK_CLKOUT1_DIV 216
#define IMX8MN_CLK_CLKOUT1 217
#define IMX8MN_CLK_CLKOUT2_SEL 218
#define IMX8MN_CLK_CLKOUT2_DIV 219
#define IMX8MN_CLK_CLKOUT2 220
#define IMX8MN_CLK_END 221
#endif

16
include/dt-bindings/clock/imx8mq-clock.h
View File

@ -431,6 +431,20 @@
#define IMX8MQ_CLK_A53_CORE 289
#define IMX8MQ_CLK_END 290
#define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV 290
#define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV 291
#define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV 292
#define IMX8MQ_CLK_MON_GPU_PLL_DIV 293
#define IMX8MQ_CLK_MON_VPU_PLL_DIV 294
#define IMX8MQ_CLK_MON_ARM_PLL_DIV 295
#define IMX8MQ_CLK_MON_SYS_PLL1_DIV 296
#define IMX8MQ_CLK_MON_SYS_PLL2_DIV 297
#define IMX8MQ_CLK_MON_SYS_PLL3_DIV 298
#define IMX8MQ_CLK_MON_DRAM_PLL_DIV 299
#define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV 300
#define IMX8MQ_CLK_MON_SEL 301
#define IMX8MQ_CLK_MON_CLK2_OUT 302
#define IMX8MQ_CLK_END 303
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */

15
include/linux/clk/imx.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2020 Freescale Semiconductor, Inc.
*
* Author: Lee Jones <lee.jones@linaro.org>
*/
#ifndef __LINUX_CLK_IMX_H
#define __LINUX_CLK_IMX_H
#include <linux/types.h>
void imx6sl_set_wait_clk(bool enter);
#endif