mirror of https://gitee.com/openkylin/linux.git
clk: renesas: cpg-mssr: Always use readl()/writel()
The Renesas CPG/MSSR driver core uses a mix of clk_readl()/clk_writel() and readl()/writel() to access the clock registers. Settle on the generic readl()/writel(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -146,12 +146,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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enable ? "ON" : "OFF");
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spin_lock_irqsave(&priv->mstp_lock, flags);
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value = clk_readl(priv->base + SMSTPCR(reg));
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value = readl(priv->base + SMSTPCR(reg));
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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clk_writel(value, priv->base + SMSTPCR(reg));
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writel(value, priv->base + SMSTPCR(reg));
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spin_unlock_irqrestore(&priv->mstp_lock, flags);
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@ -159,8 +159,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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return 0;
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for (i = 1000; i > 0; --i) {
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if (!(clk_readl(priv->base + MSTPSR(reg)) &
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bitmask))
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if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
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break;
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cpu_relax();
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}
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@ -190,7 +189,7 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
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struct cpg_mssr_priv *priv = clock->priv;
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u32 value;
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value = clk_readl(priv->base + MSTPSR(clock->index / 32));
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value = readl(priv->base + MSTPSR(clock->index / 32));
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return !(value & BIT(clock->index % 32));
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}
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