mirror of https://gitee.com/openkylin/linux.git
perf, x86: Implement arch event mask as quirk
Implement the disabling of arch events as a quirk so that we can print a message along with it. This creates some visibility into the problem space and could allow us to work on adding more work-around like the AAJ80 one. Requested-by: Ingo Molnar <mingo@elte.hu> Cc: Gleb Natapov <gleb@redhat.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/n/tip-wcja2z48wklzu1b0nkz0a5y7@git.kernel.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Peter Zijlstra
Ingo Molnar
parent
ffb871bc91
commit
c1d6f42f1a
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@ -1248,6 +1248,7 @@ static void __init pmu_check_apic(void)
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static int __init init_hw_perf_events(void)
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{
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struct x86_pmu_quirk *quirk;
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struct event_constraint *c;
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int err;
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@ -1276,8 +1277,8 @@ static int __init init_hw_perf_events(void)
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pr_cont("%s PMU driver.\n", x86_pmu.name);
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if (x86_pmu.quirks)
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x86_pmu.quirks();
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for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
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quirk->func();
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if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
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WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
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@ -261,6 +261,11 @@ union perf_capabilities {
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u64 capabilities;
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};
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struct x86_pmu_quirk {
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struct x86_pmu_quirk *next;
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void (*func)(void);
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};
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/*
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* struct x86_pmu - generic x86 pmu
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*/
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@ -299,7 +304,7 @@ struct x86_pmu {
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void (*put_event_constraints)(struct cpu_hw_events *cpuc,
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struct perf_event *event);
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struct event_constraint *event_constraints;
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void (*quirks)(void);
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struct x86_pmu_quirk *quirks;
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int perfctr_second_write;
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int (*cpu_prepare)(int cpu);
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@ -340,6 +345,15 @@ struct x86_pmu {
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struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
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};
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#define x86_add_quirk(func_) \
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do { \
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static struct x86_pmu_quirk __quirk __initdata = { \
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.func = func_, \
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}; \
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__quirk.next = x86_pmu.quirks; \
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x86_pmu.quirks = &__quirk; \
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} while (0)
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#define ERF_NO_HT_SHARING 1
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#define ERF_HAS_RSP_1 2
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@ -1519,7 +1519,7 @@ static __initconst const struct x86_pmu intel_pmu = {
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.guest_get_msrs = intel_guest_get_msrs,
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};
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static void intel_clovertown_quirks(void)
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static __init void intel_clovertown_quirk(void)
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{
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/*
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* PEBS is unreliable due to:
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@ -1545,30 +1545,61 @@ static void intel_clovertown_quirks(void)
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x86_pmu.pebs_constraints = NULL;
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}
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static void intel_sandybridge_quirks(void)
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static __init void intel_sandybridge_quirk(void)
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{
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printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
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x86_pmu.pebs = 0;
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x86_pmu.pebs_constraints = NULL;
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}
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static const int intel_event_id_to_hw_id[] __initconst = {
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PERF_COUNT_HW_CPU_CYCLES,
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PERF_COUNT_HW_INSTRUCTIONS,
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PERF_COUNT_HW_BUS_CYCLES,
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PERF_COUNT_HW_CACHE_REFERENCES,
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PERF_COUNT_HW_CACHE_MISSES,
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PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
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PERF_COUNT_HW_BRANCH_MISSES,
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static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
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{ PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
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{ PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
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{ PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
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{ PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
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{ PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
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{ PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
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{ PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
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};
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static __init void intel_arch_events_quirk(void)
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{
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int bit;
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/* disable event that reported as not presend by cpuid */
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for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
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intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
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printk(KERN_WARNING "CPUID marked event: \'%s\' unavailable\n",
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intel_arch_events_map[bit].name);
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}
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}
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static __init void intel_nehalem_quirk(void)
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{
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union cpuid10_ebx ebx;
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ebx.full = x86_pmu.events_maskl;
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if (ebx.split.no_branch_misses_retired) {
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/*
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* Erratum AAJ80 detected, we work it around by using
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* the BR_MISP_EXEC.ANY event. This will over-count
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* branch-misses, but it's still much better than the
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* architectural event which is often completely bogus:
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*/
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intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
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ebx.split.no_branch_misses_retired = 0;
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x86_pmu.events_maskl = ebx.full;
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printk(KERN_INFO "CPU erratum AAJ80 worked around\n");
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}
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}
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__init int intel_pmu_init(void)
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{
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union cpuid10_edx edx;
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union cpuid10_eax eax;
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union cpuid10_ebx ebx;
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unsigned int unused;
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int version, bit;
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int version;
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if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
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switch (boot_cpu_data.x86) {
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@ -1599,6 +1630,9 @@ __init int intel_pmu_init(void)
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x86_pmu.cntval_bits = eax.split.bit_width;
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x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
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x86_pmu.events_maskl = ebx.full;
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x86_pmu.events_mask_len = eax.split.mask_length;
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/*
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* Quirk: v2 perfmon does not report fixed-purpose events, so
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* assume at least 3 events:
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@ -1618,6 +1652,8 @@ __init int intel_pmu_init(void)
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intel_ds_init();
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x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
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/*
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* Install the hw-cache-events table:
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*/
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@ -1627,7 +1663,7 @@ __init int intel_pmu_init(void)
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break;
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case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
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x86_pmu.quirks = intel_clovertown_quirks;
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x86_add_quirk(intel_clovertown_quirk);
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case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
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case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
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case 29: /* six-core 45 nm xeon "Dunnington" */
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@ -1661,18 +1697,8 @@ __init int intel_pmu_init(void)
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/* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
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intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
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if (ebx.split.no_branch_misses_retired) {
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/*
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* Erratum AAJ80 detected, we work it around by using
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* the BR_MISP_EXEC.ANY event. This will over-count
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* branch-misses, but it's still much better than the
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* architectural event which is often completely bogus:
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*/
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intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
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ebx.split.no_branch_misses_retired = 0;
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x86_add_quirk(intel_nehalem_quirk);
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pr_cont("erratum AAJ80 worked around, ");
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}
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pr_cont("Nehalem events, ");
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break;
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@ -1712,7 +1738,7 @@ __init int intel_pmu_init(void)
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break;
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case 42: /* SandyBridge */
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x86_pmu.quirks = intel_sandybridge_quirks;
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x86_add_quirk(intel_sandybridge_quirk);
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case 45: /* SandyBridge, "Romely-EP" */
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memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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@ -1749,12 +1775,6 @@ __init int intel_pmu_init(void)
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break;
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}
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}
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x86_pmu.events_maskl = ebx.full;
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x86_pmu.events_mask_len = eax.split.mask_length;
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/* disable event that reported as not presend by cpuid */
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for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_event_id_to_hw_id))
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intel_perfmon_event_map[intel_event_id_to_hw_id[bit]] = 0;
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return 0;
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}
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