mirror of https://gitee.com/openkylin/linux.git
ALSA: hda/ca0132 - Add 8051 PLL write helper functions.
Add helper functions for the 8051 PLL PMU write verbs. Signed-off-by: Connor McAdams <conmanx360@gmail.com> Link: https://lore.kernel.org/r/20201211225504.4508-1-conmanx360@gmail.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Connor McAdams
Takashi Iwai
parent
46c3bbd982
commit
c1d8aeed83
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@ -1949,6 +1949,14 @@ static unsigned int chipio_8051_get_data(struct hda_codec *codec)
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VENDOR_CHIPIO_8051_DATA_READ, 0);
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}
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/* PLL_PMU writes share the lower address register of the 8051 exram writes. */
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static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
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{
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/* 8-bits of data. */
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
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}
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static void chipio_8051_write_exram(struct hda_codec *codec,
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unsigned int addr, unsigned int data)
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{
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@ -1977,6 +1985,26 @@ static void chipio_8051_read_exram(struct hda_codec *codec,
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*data = chipio_8051_get_data(codec);
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}
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static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
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unsigned int addr, unsigned int data)
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{
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struct ca0132_spec *spec = codec->spec;
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mutex_lock(&spec->chipio_mutex);
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chipio_8051_set_address(codec, addr & 0xff);
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chipio_8051_set_data_pll(codec, data);
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mutex_unlock(&spec->chipio_mutex);
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}
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static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
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unsigned int addr, unsigned int data)
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{
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chipio_8051_set_address(codec, addr & 0xff);
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chipio_8051_set_data_pll(codec, data);
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}
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/*
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* Enable clocks.
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*/
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@ -1985,18 +2013,11 @@ static void chipio_enable_clocks(struct hda_codec *codec)
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struct ca0132_spec *spec = codec->spec;
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mutex_lock(&spec->chipio_mutex);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
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chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
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chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
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chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
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mutex_unlock(&spec->chipio_mutex);
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}
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@ -7904,10 +7925,7 @@ static void ae5_post_dsp_register_set(struct hda_codec *codec)
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struct ca0132_spec *spec = codec->spec;
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chipio_8051_write_direct(codec, 0x93, 0x10);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
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chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
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writeb(0xff, spec->mem_base + 0x304);
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writeb(0xff, spec->mem_base + 0x304);
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@ -7949,30 +7967,11 @@ static void ae5_post_dsp_param_setup(struct hda_codec *codec)
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static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
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{
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
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chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
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chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
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chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
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chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
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chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
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}
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static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
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@ -7994,10 +7993,7 @@ static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
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chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
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chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
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ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
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@ -8090,12 +8086,8 @@ static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
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};
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(addr); i++) {
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, addr[i]);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, data[i]);
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}
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for (i = 0; i < ARRAY_SIZE(addr); i++)
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chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
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}
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static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
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@ -8111,10 +8103,7 @@ static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
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mutex_lock(&spec->chipio_mutex);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
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chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
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chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
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chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
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@ -8187,10 +8176,7 @@ static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
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{
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chipio_8051_write_direct(codec, 0x93, 0x10);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
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chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
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ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
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ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
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@ -8207,10 +8193,7 @@ static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
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ae7_post_dsp_pll_setup(codec);
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ae7_post_dsp_asi_stream_setup(codec);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
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chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
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ae7_post_dsp_asi_setup_ports(codec);
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}
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@ -9367,18 +9350,11 @@ static void ae5_register_set(struct hda_codec *codec)
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unsigned int i, cur_addr;
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unsigned char tmp[3];
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if (ca0132_quirk(spec) == QUIRK_AE7) {
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
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}
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if (ca0132_quirk(spec) == QUIRK_AE7)
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chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
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chipio_8051_write_direct(codec, 0x93, 0x10);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
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chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
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if (ca0132_quirk(spec) == QUIRK_AE7) {
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tmp[0] = 0x03;
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@ -9454,10 +9430,7 @@ static void ca0132_alt_init(struct hda_codec *codec)
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break;
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case QUIRK_AE5:
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ca0132_gpio_init(codec);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
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chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
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chipio_write(codec, 0x18b030, 0x00000020);
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snd_hda_sequence_write(codec, spec->chip_init_verbs);
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snd_hda_sequence_write(codec, spec->desktop_init_verbs);
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@ -9465,10 +9438,7 @@ static void ca0132_alt_init(struct hda_codec *codec)
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break;
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case QUIRK_AE7:
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ca0132_gpio_init(codec);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
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snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
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VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
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chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
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snd_hda_sequence_write(codec, spec->chip_init_verbs);
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snd_hda_sequence_write(codec, spec->desktop_init_verbs);
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chipio_write(codec, 0x18b008, 0x000000f8);
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