mirror of https://gitee.com/openkylin/linux.git
Adds basic support for Rockchip Cortex-A9 SoCs.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABCAAGBQJRw/9tAAoJEPOmecmc0R2B3NMH/A609NR5Yag2vftml8Gl+Iya 2k/dligAPxx/WEogXwxrCcEwFvxA3iNvD9M7MuXZ25ffFL6SgYLnxNYCU53rXRmE UBQP3OTW/5FyR3N/JGCLW4G8f6LoNWGtOaZqpMC97J4ucnWV/DtbEpoO7qlET/p0 zUsqIpFc9RGroRAmDuRRKpOuArBX5N9utH4fvpZ1XiXztIaESdCiGDFx4AN5g7Iq uujcKK1NOoj4X/LXj0j4A1ECAhpJ5W8exacdwZZnKVVwA1CpEFxQLu9ekvCYYMNC 6LWhp2/ptgRj7Tv5uVqbHJn4jKd/OM+X0Rn6HcMY1Dwhf37Oa2wPEuQ2qMzcE6A= =4BBI -----END PGP SIGNATURE----- Merge tag 'v3.11-rockchip-basics' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc From Heiko Stuebner: Adds basic support for Rockchip Cortex-A9 SoCs. * tag 'v3.11-rockchip-basics' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm: add basic support for Rockchip RK3066a boards arm: add debug uarts for rockchip rk29xx and rk3xxx series arm: Add basic clocks for Rockchip rk3066a SoCs clocksource: dw_apb_timer_of: use clocksource_of_init clocksource: dw_apb_timer_of: select DW_APB_TIMER clocksource: dw_apb_timer_of: add clock-handling clocksource: dw_apb_timer_of: enable the use the clocksource as sched clock Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c20e459fcc
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@ -5,9 +5,20 @@ Required properties:
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: IRQ line for the timer.
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- either clocks+clock-names or clock-frequency properties
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Optional properties:
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- clocks : list of clock specifiers, corresponding to entries in
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the clock-names property;
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- clock-names : should contain "timer" and "pclk" entries, matching entries
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in the clocks property.
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- clock-frequency: The frequency in HZ of the timer.
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- clock-freq: For backwards compatibility with picoxcell
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If using the clock specifiers, the pclk clock is optional, as not all
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systems may use one.
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Example:
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timer1: timer@ffc09000 {
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@ -23,3 +34,11 @@ Example:
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clock-frequency = <200000000>;
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reg = <0xffd00000 0x1000>;
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};
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timer3: timer@ffe00000 {
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compatible = "snps,dw-apb-timer-osc";
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interrupts = <0 170 4>;
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reg = <0xffe00000 0x1000>;
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clocks = <&timer_clk>, <&timer_pclk>;
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clock-names = "timer", "pclk";
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};
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@ -982,6 +982,8 @@ source "arch/arm/mach-mmp/Kconfig"
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source "arch/arm/mach-realview/Kconfig"
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source "arch/arm/mach-rockchip/Kconfig"
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source "arch/arm/mach-sa1100/Kconfig"
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source "arch/arm/plat-samsung/Kconfig"
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@ -399,6 +399,13 @@ choice
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their output to the standard serial port on the RealView
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PB1176 platform.
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config DEBUG_ROCKCHIP_UART
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bool "Kernel low-level debugging messages via Rockchip UART"
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depends on ARCH_ROCKCHIP
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help
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Say Y here if you want kernel low-level debugging support
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on Rockchip based platforms.
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config DEBUG_S3C_UART0
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depends on PLAT_SAMSUNG
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select DEBUG_EXYNOS_UART if ARCH_EXYNOS
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@ -641,6 +648,32 @@ choice
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bool "Zoom2/3 UART"
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endchoice
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choice
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prompt "Low-level debug console UART"
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depends on DEBUG_ROCKCHIP_UART
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config DEBUG_RK29_UART0
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bool "RK29 UART0"
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config DEBUG_RK29_UART1
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bool "RK29 UART1"
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config DEBUG_RK29_UART2
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bool "RK29 UART2"
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config DEBUG_RK3X_UART0
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bool "RK3X UART0"
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config DEBUG_RK3X_UART1
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bool "RK3X UART1"
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config DEBUG_RK3X_UART2
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bool "RK3X UART2"
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config DEBUG_RK3X_UART3
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bool "RK3X UART3"
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endchoice
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choice
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prompt "Low-level debug console UART"
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depends on DEBUG_LL && DEBUG_TEGRA_UART
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@ -697,6 +730,7 @@ config DEBUG_LL_INCLUDE
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default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
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default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
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DEBUG_MMP_UART3
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default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART
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default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
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default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
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default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
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@ -172,6 +172,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
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machine-$(CONFIG_ARCH_PRIMA2) += prima2
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machine-$(CONFIG_ARCH_PXA) += pxa
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machine-$(CONFIG_ARCH_REALVIEW) += realview
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machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
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machine-$(CONFIG_ARCH_RPC) += rpc
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machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx
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machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
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@ -0,0 +1,299 @@
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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compatible = "fixed-clock";
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clock-frequency = <0>;
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#clock-cells = <0>;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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dummy48m: dummy48m {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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dummy150m: dummy150m {
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compatible = "fixed-clock";
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clock-frequency = <150000000>;
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#clock-cells = <0>;
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};
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clk_gates0: gate-clk@200000d0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d0 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_core_periph", "gate_cpu_gpll",
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"gate_ddrphy", "gate_aclk_cpu",
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"gate_hclk_cpu", "gate_pclk_cpu",
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"gate_atclk_cpu", "gate_i2s0",
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"gate_i2s0_frac", "gate_i2s1",
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"gate_i2s1_frac", "gate_i2s2",
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"gate_i2s2_frac", "gate_spdif",
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"gate_spdif_frac", "gate_testclk";
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#clock-cells = <1>;
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};
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clk_gates1: gate-clk@200000d4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d4 0x4>;
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clocks = <&xin24m>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&dummy>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>;
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clock-output-names =
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"gate_timer0", "gate_timer1",
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"gate_timer2", "gate_jtag",
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"gate_aclk_lcdc1_src", "gate_otgphy0",
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"gate_otgphy1", "gate_ddr_gpll",
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"gate_uart0", "gate_frac_uart0",
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"gate_uart1", "gate_frac_uart1",
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"gate_uart2", "gate_frac_uart2",
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"gate_uart3", "gate_frac_uart3";
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#clock-cells = <1>;
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};
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clk_gates2: gate-clk@200000d8 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d8 0x4>;
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clocks = <&clk_gates2 1>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&clk_gates2 3>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy48m>,
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<&dummy>, <&dummy48m>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_periph_src", "gate_aclk_periph",
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"gate_hclk_periph", "gate_pclk_periph",
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"gate_smc", "gate_mac",
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"gate_hsadc", "gate_hsadc_frac",
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"gate_saradc", "gate_spi0",
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"gate_spi1", "gate_mmc0",
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"gate_mac_lbtest", "gate_mmc1",
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"gate_emmc", "gate_tsadc";
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#clock-cells = <1>;
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};
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clk_gates3: gate-clk@200000dc {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000dc 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
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"gate_dclk_lcdc1", "gate_pclkin_cif0",
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"gate_pclkin_cif1", "reserved",
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"reserved", "gate_cif0_out",
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"gate_cif1_out", "gate_aclk_vepu",
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"gate_hclk_vepu", "gate_aclk_vdpu",
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"gate_hclk_vdpu", "gate_gpu_src",
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"reserved", "gate_xin27m";
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#clock-cells = <1>;
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};
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clk_gates4: gate-clk@200000e0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e0 0x4>;
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clocks = <&clk_gates2 2>, <&clk_gates2 3>,
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<&clk_gates2 1>, <&clk_gates2 1>,
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<&clk_gates2 1>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates2 2>,
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<&clk_gates0 4>, <&clk_gates0 4>,
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<&clk_gates0 3>, <&clk_gates0 3>,
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<&clk_gates0 3>, <&clk_gates2 3>,
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<&clk_gates0 4>;
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clock-output-names =
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"gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
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"gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
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"gate_aclk_pei_niu", "gate_hclk_usb_peri",
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"gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
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"gate_hclk_cpubus", "gate_hclk_ahb2apb",
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"gate_aclk_strc_sys", "gate_aclk_l2mem_con",
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"gate_aclk_intmem", "gate_pclk_tsadc",
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"gate_hclk_hdmi";
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#clock-cells = <1>;
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};
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clk_gates5: gate-clk@200000e4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e4 0x4>;
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clocks = <&clk_gates0 3>, <&clk_gates2 1>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates0 4>, <&clk_gates0 5>,
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<&clk_gates2 1>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates4 5>,
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<&clk_gates4 5>, <&dummy>;
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clock-output-names =
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"gate_aclk_dmac1", "gate_aclk_dmac2",
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"gate_pclk_efuse", "gate_pclk_tzpc",
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"gate_pclk_grf", "gate_pclk_pmu",
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"gate_hclk_rom", "gate_pclk_ddrupctl",
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"gate_aclk_smc", "gate_hclk_nandc",
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"gate_hclk_mmc0", "gate_hclk_mmc1",
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"gate_hclk_emmc", "gate_hclk_otg0",
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"gate_hclk_otg1", "gate_aclk_gpu";
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#clock-cells = <1>;
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};
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clk_gates6: gate-clk@200000e8 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e8 0x4>;
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clocks = <&clk_gates3 0>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates1 4>,
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<&clk_gates0 4>, <&clk_gates3 0>,
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<&clk_gates0 4>, <&clk_gates1 4>,
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<&clk_gates3 0>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates1 4>,
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<&clk_gates0 4>, <&clk_gates3 0>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_aclk_lcdc0", "gate_hclk_lcdc0",
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"gate_hclk_lcdc1", "gate_aclk_lcdc1",
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"gate_hclk_cif0", "gate_aclk_cif0",
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"gate_hclk_cif1", "gate_aclk_cif1",
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"gate_aclk_ipp", "gate_hclk_ipp",
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"gate_hclk_rga", "gate_aclk_rga",
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"gate_hclk_vio_bus", "gate_aclk_vio0",
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"gate_aclk_vcodec", "gate_shclk_vio_h2h";
|
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#clock-cells = <1>;
|
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};
|
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|
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clk_gates7: gate-clk@200000ec {
|
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compatible = "rockchip,rk2928-gate-clk";
|
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reg = <0x200000ec 0x4>;
|
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clocks = <&clk_gates2 2>, <&clk_gates0 4>,
|
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<&clk_gates0 4>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates2 2>,
|
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<&clk_gates2 2>, <&clk_gates0 5>,
|
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<&clk_gates0 5>, <&clk_gates0 5>,
|
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<&clk_gates0 5>, <&clk_gates2 3>,
|
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<&clk_gates2 3>, <&clk_gates2 3>,
|
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<&clk_gates2 3>, <&clk_gates2 3>;
|
||||
|
||||
clock-output-names =
|
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"gate_hclk_emac", "gate_hclk_spdif",
|
||||
"gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
|
||||
"gate_hclk_i2s_8ch", "gate_hclk_hsadc",
|
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"gate_hclk_pidf", "gate_pclk_timer0",
|
||||
"gate_pclk_timer1", "gate_pclk_timer2",
|
||||
"gate_pclk_pwm01", "gate_pclk_pwm23",
|
||||
"gate_pclk_spi0", "gate_pclk_spi1",
|
||||
"gate_pclk_saradc", "gate_pclk_wdt";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clk_gates8: gate-clk@200000f0 {
|
||||
compatible = "rockchip,rk2928-gate-clk";
|
||||
reg = <0x200000f0 0x4>;
|
||||
clocks = <&clk_gates0 5>, <&clk_gates0 5>,
|
||||
<&clk_gates2 3>, <&clk_gates2 3>,
|
||||
<&clk_gates0 5>, <&clk_gates0 5>,
|
||||
<&clk_gates2 3>, <&clk_gates2 3>,
|
||||
<&clk_gates2 3>, <&clk_gates0 5>,
|
||||
<&clk_gates0 5>, <&clk_gates0 5>,
|
||||
<&clk_gates2 3>, <&clk_gates2 3>,
|
||||
<&dummy>, <&clk_gates0 5>;
|
||||
|
||||
clock-output-names =
|
||||
"gate_pclk_uart0", "gate_pclk_uart1",
|
||||
"gate_pclk_uart2", "gate_pclk_uart3",
|
||||
"gate_pclk_i2c0", "gate_pclk_i2c1",
|
||||
"gate_pclk_i2c2", "gate_pclk_i2c3",
|
||||
"gate_pclk_i2c4", "gate_pclk_gpio0",
|
||||
"gate_pclk_gpio1", "gate_pclk_gpio2",
|
||||
"gate_pclk_gpio3", "gate_pclk_gpio4",
|
||||
"reserved", "gate_pclk_gpio6";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clk_gates9: gate-clk@200000f4 {
|
||||
compatible = "rockchip,rk2928-gate-clk";
|
||||
reg = <0x200000f4 0x4>;
|
||||
clocks = <&dummy>, <&clk_gates0 5>,
|
||||
<&dummy>, <&dummy>,
|
||||
<&dummy>, <&clk_gates1 4>,
|
||||
<&clk_gates0 5>, <&dummy>,
|
||||
<&dummy>, <&dummy>,
|
||||
<&dummy>;
|
||||
|
||||
clock-output-names =
|
||||
"gate_clk_core_dbg", "gate_pclk_dbg",
|
||||
"gate_clk_trace", "gate_atclk",
|
||||
"gate_clk_l2c", "gate_aclk_vio1",
|
||||
"gate_pclk_publ", "gate_aclk_intmem0",
|
||||
"gate_aclk_intmem1", "gate_aclk_intmem2",
|
||||
"gate_aclk_intmem3";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
/*
|
||||
* Copyright (c) 2013 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "skeleton.dtsi"
|
||||
#include "rk3066a-clocks.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3066a";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
gic: interrupt-controller@1013d000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x1013d000 0x1000>,
|
||||
<0x1013c100 0x0100>;
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@10138000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x10138000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
local-timer@1013c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1013c600 0x20>;
|
||||
interrupts = <GIC_PPI 13 0x304>;
|
||||
clocks = <&dummy150m>;
|
||||
};
|
||||
|
||||
timer@20038000 {
|
||||
compatible = "snps,dw-apb-timer-osc";
|
||||
reg = <0x20038000 0x100>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates1 0>, <&clk_gates7 7>;
|
||||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
timer@2003a000 {
|
||||
compatible = "snps,dw-apb-timer-osc";
|
||||
reg = <0x2003a000 0x100>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates1 1>, <&clk_gates7 8>;
|
||||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
timer@2000e000 {
|
||||
compatible = "snps,dw-apb-timer-osc";
|
||||
reg = <0x2000e000 0x100>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates1 2>, <&clk_gates7 9>;
|
||||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
pinctrl@20008000 {
|
||||
compatible = "rockchip,rk3066a-pinctrl";
|
||||
reg = <0x20008000 0x150>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@20034000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20034000 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 9>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@2003c000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003c000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 10>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio2@2003e000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2003e000 0x100>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 11>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio3@20080000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20080000 0x100>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 12>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio4@20084000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x20084000 0x100>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 13>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio6@2000a000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x2000a000 0x100>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_gates8 15>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_default: pcfg_pull_default {
|
||||
bias-pull-pin-default;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg_pull_none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
};
|
||||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart3_cts: uart3-cts {
|
||||
rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart3_rts: uart3-rts {
|
||||
rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
sd0 {
|
||||
sd0_clk: sd0-clk {
|
||||
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_cmd: sd0-cmd {
|
||||
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_cd: sd0-cd {
|
||||
rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_wp: sd0-wp {
|
||||
rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_bus1: sd0-bus-width1 {
|
||||
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd0_bus4: sd0-bus-width4 {
|
||||
rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
sd1 {
|
||||
sd1_clk: sd1-clk {
|
||||
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_cmd: sd1-cmd {
|
||||
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_cd: sd1-cd {
|
||||
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_wp: sd1-wp {
|
||||
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_bus1: sd1-bus-width1 {
|
||||
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sd1_bus4: sd1-bus-width4 {
|
||||
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
|
||||
rockchip,config = <&pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&clk_gates1 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10126000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10126000 0x400>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&clk_gates1 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@20064000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20064000 0x400>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&clk_gates1 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@20068000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20068000 0x400>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&clk_gates1 14>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc@10214000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
reg = <0x10214000 0x1000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clocks = <&clk_gates5 10>, <&clk_gates2 11>;
|
||||
clock-names = "biu", "ciu";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dwmmc@10218000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
reg = <0x10218000 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clocks = <&clk_gates5 11>, <&clk_gates2 13>;
|
||||
clock-names = "biu", "ciu";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Early serial output macro for Rockchip SoCs
|
||||
*
|
||||
* Copyright (C) 2012 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_DEBUG_RK29_UART0)
|
||||
#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000
|
||||
#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000
|
||||
#elif defined(CONFIG_DEBUG_RK29_UART1)
|
||||
#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
|
||||
#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
|
||||
#elif defined(CONFIG_DEBUG_RK29_UART2)
|
||||
#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
|
||||
#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
|
||||
#elif defined(CONFIG_DEBUG_RK3X_UART0)
|
||||
#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000
|
||||
#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000
|
||||
#elif defined(CONFIG_DEBUG_RK3X_UART1)
|
||||
#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000
|
||||
#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000
|
||||
#elif defined(CONFIG_DEBUG_RK3X_UART2)
|
||||
#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
|
||||
#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
|
||||
#elif defined(CONFIG_DEBUG_RK3X_UART3)
|
||||
#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
|
||||
#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
|
||||
#endif
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE
|
||||
ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
|
|
@ -4,7 +4,6 @@ config ARCH_PICOXCELL
|
|||
select ARM_PATCH_PHYS_VIRT
|
||||
select ARM_VIC
|
||||
select CPU_V6K
|
||||
select DW_APB_TIMER
|
||||
select DW_APB_TIMER_OF
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_TCM
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/dw_apb_timer.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
|
@ -88,7 +87,6 @@ DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
|
|||
.map_io = picoxcell_map_io,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = irqchip_init,
|
||||
.init_time = dw_apb_timer_init,
|
||||
.init_machine = picoxcell_init_machine,
|
||||
.dt_compat = picoxcell_dt_match,
|
||||
.restart = picoxcell_wdt_restart,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,16 @@
|
|||
config ARCH_ROCKCHIP
|
||||
bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7
|
||||
select PINCTRL
|
||||
select PINCTRL_ROCKCHIP
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARM_GIC
|
||||
select CACHE_L2X0
|
||||
select HAVE_ARM_TWD if LOCAL_TIMERS
|
||||
select HAVE_SMP
|
||||
select LOCAL_TIMERS if SMP
|
||||
select COMMON_CLK
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select DW_APB_TIMER_OF
|
||||
help
|
||||
Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
|
||||
containing the RK2928, RK30xx and RK31xx series.
|
||||
|
|
@ -0,0 +1 @@
|
|||
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Device Tree support for Rockchip SoCs
|
||||
*
|
||||
* Copyright (c) 2013 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/dw_apb_timer.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
static void __init rockchip_timer_init(void)
|
||||
{
|
||||
of_clk_init(NULL);
|
||||
clocksource_of_init();
|
||||
}
|
||||
|
||||
static void __init rockchip_dt_init(void)
|
||||
{
|
||||
l2x0_of_init(0, ~0UL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char * const rockchip_board_dt_compat[] = {
|
||||
"rockchip,rk2928",
|
||||
"rockchip,rk3066a",
|
||||
"rockchip,rk3066b",
|
||||
"rockchip,rk3188",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
|
||||
.init_machine = rockchip_dt_init,
|
||||
.init_time = rockchip_timer_init,
|
||||
.dt_compat = rockchip_board_dt_compat,
|
||||
MACHINE_END
|
||||
|
|
@ -7,7 +7,6 @@ config ARCH_SOCFPGA
|
|||
select CLKDEV_LOOKUP
|
||||
select COMMON_CLK
|
||||
select CPU_V7
|
||||
select DW_APB_TIMER
|
||||
select DW_APB_TIMER_OF
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select GPIO_PL061 if GPIOLIB
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@
|
|||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include <linux/dw_apb_timer.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_address.h>
|
||||
|
|
@ -120,7 +119,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
|
|||
.smp = smp_ops(socfpga_smp_ops),
|
||||
.map_io = socfpga_map_io,
|
||||
.init_irq = socfpga_init_irq,
|
||||
.init_time = dw_apb_timer_init,
|
||||
.init_machine = socfpga_cyclone5_init,
|
||||
.restart = socfpga_cyclone5_restart,
|
||||
.dt_compat = altera_dt_match,
|
||||
|
|
|
|||
|
|
@ -21,6 +21,8 @@ config DW_APB_TIMER
|
|||
|
||||
config DW_APB_TIMER_OF
|
||||
bool
|
||||
select DW_APB_TIMER
|
||||
select CLKSRC_OF
|
||||
|
||||
config ARMADA_370_XP_TIMER
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/sched_clock.h>
|
||||
|
|
@ -27,14 +28,37 @@
|
|||
static void timer_get_base_and_rate(struct device_node *np,
|
||||
void __iomem **base, u32 *rate)
|
||||
{
|
||||
struct clk *timer_clk;
|
||||
struct clk *pclk;
|
||||
|
||||
*base = of_iomap(np, 0);
|
||||
|
||||
if (!*base)
|
||||
panic("Unable to map regs for %s", np->name);
|
||||
|
||||
/*
|
||||
* Not all implementations use a periphal clock, so don't panic
|
||||
* if it's not present
|
||||
*/
|
||||
pclk = of_clk_get_by_name(np, "pclk");
|
||||
if (!IS_ERR(pclk))
|
||||
if (clk_prepare_enable(pclk))
|
||||
pr_warn("pclk for %s is present, but could not be activated\n",
|
||||
np->name);
|
||||
|
||||
timer_clk = of_clk_get_by_name(np, "timer");
|
||||
if (IS_ERR(timer_clk))
|
||||
goto try_clock_freq;
|
||||
|
||||
if (!clk_prepare_enable(timer_clk)) {
|
||||
*rate = clk_get_rate(timer_clk);
|
||||
return;
|
||||
}
|
||||
|
||||
try_clock_freq:
|
||||
if (of_property_read_u32(np, "clock-freq", rate) &&
|
||||
of_property_read_u32(np, "clock-frequency", rate))
|
||||
panic("No clock-frequency property for %s", np->name);
|
||||
panic("No clock nor clock-frequency property for %s", np->name);
|
||||
}
|
||||
|
||||
static void add_clockevent(struct device_node *event_timer)
|
||||
|
|
@ -57,6 +81,9 @@ static void add_clockevent(struct device_node *event_timer)
|
|||
dw_apb_clockevent_register(ced);
|
||||
}
|
||||
|
||||
static void __iomem *sched_io_base;
|
||||
static u32 sched_rate;
|
||||
|
||||
static void add_clocksource(struct device_node *source_timer)
|
||||
{
|
||||
void __iomem *iobase;
|
||||
|
|
@ -71,9 +98,15 @@ static void add_clocksource(struct device_node *source_timer)
|
|||
|
||||
dw_apb_clocksource_start(cs);
|
||||
dw_apb_clocksource_register(cs);
|
||||
}
|
||||
|
||||
static void __iomem *sched_io_base;
|
||||
/*
|
||||
* Fallback to use the clocksource as sched_clock if no separate
|
||||
* timer is found. sched_io_base then points to the current_value
|
||||
* register of the clocksource timer.
|
||||
*/
|
||||
sched_io_base = iobase + 0x04;
|
||||
sched_rate = rate;
|
||||
}
|
||||
|
||||
static u32 read_sched_clock(void)
|
||||
{
|
||||
|
|
@ -89,39 +122,37 @@ static const struct of_device_id sptimer_ids[] __initconst = {
|
|||
static void init_sched_clock(void)
|
||||
{
|
||||
struct device_node *sched_timer;
|
||||
u32 rate;
|
||||
|
||||
sched_timer = of_find_matching_node(NULL, sptimer_ids);
|
||||
if (!sched_timer)
|
||||
panic("No RTC for sched clock to use");
|
||||
if (sched_timer) {
|
||||
timer_get_base_and_rate(sched_timer, &sched_io_base,
|
||||
&sched_rate);
|
||||
of_node_put(sched_timer);
|
||||
}
|
||||
|
||||
timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
|
||||
of_node_put(sched_timer);
|
||||
|
||||
setup_sched_clock(read_sched_clock, 32, rate);
|
||||
setup_sched_clock(read_sched_clock, 32, sched_rate);
|
||||
}
|
||||
|
||||
static const struct of_device_id osctimer_ids[] __initconst = {
|
||||
{ .compatible = "picochip,pc3x2-timer" },
|
||||
{ .compatible = "snps,dw-apb-timer-osc" },
|
||||
{},
|
||||
};
|
||||
|
||||
void __init dw_apb_timer_init(void)
|
||||
static int num_called;
|
||||
static void __init dw_apb_timer_init(struct device_node *timer)
|
||||
{
|
||||
struct device_node *event_timer, *source_timer;
|
||||
switch (num_called) {
|
||||
case 0:
|
||||
pr_debug("%s: found clockevent timer\n", __func__);
|
||||
add_clockevent(timer);
|
||||
of_node_put(timer);
|
||||
break;
|
||||
case 1:
|
||||
pr_debug("%s: found clocksource timer\n", __func__);
|
||||
add_clocksource(timer);
|
||||
of_node_put(timer);
|
||||
init_sched_clock();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
event_timer = of_find_matching_node(NULL, osctimer_ids);
|
||||
if (!event_timer)
|
||||
panic("No timer for clockevent");
|
||||
add_clockevent(event_timer);
|
||||
|
||||
source_timer = of_find_matching_node(event_timer, osctimer_ids);
|
||||
if (!source_timer)
|
||||
panic("No timer for clocksource");
|
||||
add_clocksource(source_timer);
|
||||
|
||||
of_node_put(source_timer);
|
||||
|
||||
init_sched_clock();
|
||||
num_called++;
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
|
||||
CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer-osc", dw_apb_timer_init);
|
||||
|
|
|
|||
|
|
@ -53,5 +53,4 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
|
|||
cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
|
||||
void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
|
||||
|
||||
extern void dw_apb_timer_init(void);
|
||||
#endif /* __DW_APB_TIMER_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue