mirror of https://gitee.com/openkylin/linux.git
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor
The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Lars-Peter Clausen
Jonathan Cameron
parent
d0dc4c80b9
commit
c2b7720a79
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@ -1228,8 +1228,15 @@ config XILINX_XADC
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select IIO_BUFFER
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select IIO_TRIGGERED_BUFFER
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help
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Say yes here to have support for the Xilinx XADC. The driver does support
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both the ZYNQ interface to the XADC as well as the AXI-XADC interface.
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Say yes here to have support for the Xilinx 7 Series XADC or
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UltraScale/UltraScale+ System Management Wizard.
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For the 7 Series the driver does support both the ZYNQ interface
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to the XADC as well as the AXI-XADC interface.
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The driver also support the Xilinx System Management Wizard IP core
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that can be used to access the System Monitor ADC on the Xilinx
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UltraScale and UltraScale+ FPGAs.
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The driver can also be build as a module. If so, the module will be called
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xilinx-xadc.
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@ -92,7 +92,12 @@ static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
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#define XADC_AXI_REG_GIER 0x5c
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#define XADC_AXI_REG_IPISR 0x60
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#define XADC_AXI_REG_IPIER 0x68
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#define XADC_AXI_ADC_REG_OFFSET 0x200
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/* 7 Series */
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#define XADC_7S_AXI_ADC_REG_OFFSET 0x200
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/* UltraScale */
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#define XADC_US_AXI_ADC_REG_OFFSET 0x400
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#define XADC_AXI_RESET_MAGIC 0xa
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#define XADC_AXI_GIER_ENABLE BIT(31)
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@ -447,6 +452,12 @@ static const struct xadc_ops xadc_zynq_ops = {
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.get_dclk_rate = xadc_zynq_get_dclk_rate,
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.interrupt_handler = xadc_zynq_interrupt_handler,
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.update_alarm = xadc_zynq_update_alarm,
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.type = XADC_TYPE_S7,
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};
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static const unsigned int xadc_axi_reg_offsets[] = {
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[XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
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[XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
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};
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static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
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@ -454,7 +465,8 @@ static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
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{
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uint32_t val32;
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xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32);
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xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
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&val32);
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*val = val32 & 0xffff;
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return 0;
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@ -463,7 +475,8 @@ static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
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static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
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uint16_t val)
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{
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xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val);
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xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
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val);
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return 0;
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}
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@ -541,7 +554,7 @@ static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
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return clk_get_rate(xadc->clk);
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}
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static const struct xadc_ops xadc_axi_ops = {
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static const struct xadc_ops xadc_7s_axi_ops = {
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.read = xadc_axi_read_adc_reg,
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.write = xadc_axi_write_adc_reg,
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.setup = xadc_axi_setup,
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@ -549,6 +562,18 @@ static const struct xadc_ops xadc_axi_ops = {
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.update_alarm = xadc_axi_update_alarm,
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.interrupt_handler = xadc_axi_interrupt_handler,
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.flags = XADC_FLAGS_BUFFERED,
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.type = XADC_TYPE_S7,
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};
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static const struct xadc_ops xadc_us_axi_ops = {
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.read = xadc_axi_read_adc_reg,
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.write = xadc_axi_write_adc_reg,
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.setup = xadc_axi_setup,
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.get_dclk_rate = xadc_axi_get_dclk,
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.update_alarm = xadc_axi_update_alarm,
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.interrupt_handler = xadc_axi_interrupt_handler,
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.flags = XADC_FLAGS_BUFFERED,
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.type = XADC_TYPE_US,
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};
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static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
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@ -732,6 +757,15 @@ static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
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{
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uint16_t val;
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/*
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* As per datasheet the power-down bits are don't care in the
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* UltraScale, but as per reality setting the power-down bit for the
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* non-existing ADC-B powers down the main ADC, so just return and don't
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* do anything.
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*/
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if (xadc->ops->type == XADC_TYPE_US)
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return 0;
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/* Powerdown the ADC-B when it is not needed. */
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switch (seq_mode) {
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case XADC_CONF1_SEQ_SIMULTANEOUS:
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@ -751,6 +785,10 @@ static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
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{
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unsigned int aux_scan_mode = scan_mode >> 16;
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/* UltraScale has only one ADC and supports only continuous mode */
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if (xadc->ops->type == XADC_TYPE_US)
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return XADC_CONF1_SEQ_CONTINUOUS;
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if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
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return XADC_CONF1_SEQ_SIMULTANEOUS;
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@ -863,6 +901,7 @@ static int xadc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val, int *val2, long info)
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{
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struct xadc *xadc = iio_priv(indio_dev);
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unsigned int bits = chan->scan_type.realbits;
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uint16_t val16;
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int ret;
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@ -874,17 +913,17 @@ static int xadc_read_raw(struct iio_dev *indio_dev,
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if (ret < 0)
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return ret;
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val16 >>= 4;
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val16 >>= chan->scan_type.shift;
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if (chan->scan_type.sign == 'u')
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*val = val16;
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else
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*val = sign_extend32(val16, 11);
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*val = sign_extend32(val16, bits - 1);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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switch (chan->type) {
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case IIO_VOLTAGE:
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/* V = (val * 3.0) / 4096 */
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/* V = (val * 3.0) / 2**bits */
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switch (chan->address) {
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case XADC_REG_VCCINT:
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case XADC_REG_VCCAUX:
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@ -900,19 +939,19 @@ static int xadc_read_raw(struct iio_dev *indio_dev,
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*val = 1000;
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break;
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}
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*val2 = 12;
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*val2 = chan->scan_type.realbits;
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return IIO_VAL_FRACTIONAL_LOG2;
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case IIO_TEMP:
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/* Temp in C = (val * 503.975) / 4096 - 273.15 */
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/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
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*val = 503975;
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*val2 = 12;
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*val2 = bits;
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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case IIO_CHAN_INFO_OFFSET:
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/* Only the temperature channel has an offset */
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*val = -((273150 << 12) / 503975);
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*val = -((273150 << bits) / 503975);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SAMP_FREQ:
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ret = xadc_read_samplerate(xadc);
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@ -1001,7 +1040,7 @@ static const struct iio_event_spec xadc_voltage_events[] = {
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},
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};
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#define XADC_CHAN_TEMP(_chan, _scan_index, _addr) { \
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#define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
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.type = IIO_TEMP, \
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.indexed = 1, \
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.channel = (_chan), \
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@ -1015,14 +1054,14 @@ static const struct iio_event_spec xadc_voltage_events[] = {
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.scan_index = (_scan_index), \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 12, \
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.realbits = (_bits), \
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.storagebits = 16, \
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.shift = 4, \
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.shift = 16 - (_bits), \
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.endianness = IIO_CPU, \
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}, \
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}
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#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) { \
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#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = (_chan), \
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@ -1035,41 +1074,82 @@ static const struct iio_event_spec xadc_voltage_events[] = {
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.scan_index = (_scan_index), \
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.scan_type = { \
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.sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
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.realbits = 12, \
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.realbits = (_bits), \
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.storagebits = 16, \
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.shift = 4, \
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.shift = 16 - (_bits), \
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.endianness = IIO_CPU, \
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}, \
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.extend_name = _ext, \
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}
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static const struct iio_chan_spec xadc_channels[] = {
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XADC_CHAN_TEMP(0, 8, XADC_REG_TEMP),
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XADC_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
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XADC_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
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XADC_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
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XADC_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
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XADC_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
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XADC_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
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XADC_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
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XADC_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
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XADC_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
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XADC_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
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XADC_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
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XADC_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
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XADC_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
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XADC_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
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XADC_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
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XADC_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
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XADC_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
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XADC_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
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XADC_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
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XADC_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
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XADC_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
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XADC_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
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XADC_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
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XADC_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
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XADC_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
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/* 7 Series */
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#define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
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XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
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#define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
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XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
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static const struct iio_chan_spec xadc_7s_channels[] = {
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XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
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XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
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XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
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XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
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XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
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XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
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XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
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XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
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XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
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XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
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XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
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XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
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XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
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XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
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XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
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XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
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XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
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XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
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XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
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XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
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XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
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XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
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XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
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XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
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XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
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XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
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};
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/* UltraScale */
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#define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
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XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
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#define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
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XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
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static const struct iio_chan_spec xadc_us_channels[] = {
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XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
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XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
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XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
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XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
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XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
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XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
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XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
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XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
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XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
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XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
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XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
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XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
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XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
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XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
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XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
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XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
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XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
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XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
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XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
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XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
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XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
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XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
|
||||
XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
|
||||
XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
|
||||
XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
|
||||
XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
|
||||
};
|
||||
|
||||
static const struct iio_info xadc_info = {
|
||||
|
|
@ -1083,8 +1163,16 @@ static const struct iio_info xadc_info = {
|
|||
};
|
||||
|
||||
static const struct of_device_id xadc_of_match_table[] = {
|
||||
{ .compatible = "xlnx,zynq-xadc-1.00.a", (void *)&xadc_zynq_ops },
|
||||
{ .compatible = "xlnx,axi-xadc-1.00.a", (void *)&xadc_axi_ops },
|
||||
{
|
||||
.compatible = "xlnx,zynq-xadc-1.00.a",
|
||||
.data = &xadc_zynq_ops
|
||||
}, {
|
||||
.compatible = "xlnx,axi-xadc-1.00.a",
|
||||
.data = &xadc_7s_axi_ops
|
||||
}, {
|
||||
.compatible = "xlnx,system-management-wiz-1.3",
|
||||
.data = &xadc_us_axi_ops
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, xadc_of_match_table);
|
||||
|
|
@ -1094,8 +1182,10 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
|
|||
{
|
||||
struct device *dev = indio_dev->dev.parent;
|
||||
struct xadc *xadc = iio_priv(indio_dev);
|
||||
const struct iio_chan_spec *channel_templates;
|
||||
struct iio_chan_spec *channels, *chan;
|
||||
struct device_node *chan_node, *child;
|
||||
unsigned int max_channels;
|
||||
unsigned int num_channels;
|
||||
const char *external_mux;
|
||||
u32 ext_mux_chan;
|
||||
|
|
@ -1136,9 +1226,15 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
|
|||
|
||||
*conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
|
||||
}
|
||||
|
||||
channels = devm_kmemdup(dev, xadc_channels,
|
||||
sizeof(xadc_channels), GFP_KERNEL);
|
||||
if (xadc->ops->type == XADC_TYPE_S7) {
|
||||
channel_templates = xadc_7s_channels;
|
||||
max_channels = ARRAY_SIZE(xadc_7s_channels);
|
||||
} else {
|
||||
channel_templates = xadc_us_channels;
|
||||
max_channels = ARRAY_SIZE(xadc_us_channels);
|
||||
}
|
||||
channels = devm_kmemdup(dev, channel_templates,
|
||||
sizeof(channels[0]) * max_channels, GFP_KERNEL);
|
||||
if (!channels)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -1148,7 +1244,7 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
|
|||
chan_node = of_get_child_by_name(np, "xlnx,channels");
|
||||
if (chan_node) {
|
||||
for_each_child_of_node(chan_node, child) {
|
||||
if (num_channels >= ARRAY_SIZE(xadc_channels)) {
|
||||
if (num_channels >= max_channels) {
|
||||
of_node_put(child);
|
||||
break;
|
||||
}
|
||||
|
|
@ -1184,6 +1280,11 @@ static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const char * const xadc_type_names[] = {
|
||||
[XADC_TYPE_S7] = "xadc",
|
||||
[XADC_TYPE_US] = "xilinx-system-monitor",
|
||||
};
|
||||
|
||||
static int xadc_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *id;
|
||||
|
|
@ -1222,7 +1323,7 @@ static int xadc_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(xadc->base))
|
||||
return PTR_ERR(xadc->base);
|
||||
|
||||
indio_dev->name = "xadc";
|
||||
indio_dev->name = xadc_type_names[xadc->ops->type];
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
indio_dev->info = &xadc_info;
|
||||
|
||||
|
|
|
|||
|
|
@ -155,9 +155,6 @@ int xadc_write_event_config(struct iio_dev *indio_dev,
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Register value is msb aligned, the lower 4 bits are ignored */
|
||||
#define XADC_THRESHOLD_VALUE_SHIFT 4
|
||||
|
||||
int xadc_read_event_value(struct iio_dev *indio_dev,
|
||||
const struct iio_chan_spec *chan, enum iio_event_type type,
|
||||
enum iio_event_direction dir, enum iio_event_info info,
|
||||
|
|
@ -177,7 +174,8 @@ int xadc_read_event_value(struct iio_dev *indio_dev,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
*val >>= XADC_THRESHOLD_VALUE_SHIFT;
|
||||
/* MSB aligned */
|
||||
*val >>= 16 - chan->scan_type.realbits;
|
||||
|
||||
return IIO_VAL_INT;
|
||||
}
|
||||
|
|
@ -191,7 +189,8 @@ int xadc_write_event_value(struct iio_dev *indio_dev,
|
|||
struct xadc *xadc = iio_priv(indio_dev);
|
||||
int ret = 0;
|
||||
|
||||
val <<= XADC_THRESHOLD_VALUE_SHIFT;
|
||||
/* MSB aligned */
|
||||
val <<= 16 - chan->scan_type.realbits;
|
||||
|
||||
if (val < 0 || val > 0xffff)
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -70,6 +70,11 @@ struct xadc {
|
|||
int irq;
|
||||
};
|
||||
|
||||
enum xadc_type {
|
||||
XADC_TYPE_S7, /* Series 7 */
|
||||
XADC_TYPE_US, /* UltraScale and UltraScale+ */
|
||||
};
|
||||
|
||||
struct xadc_ops {
|
||||
int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val);
|
||||
int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val);
|
||||
|
|
@ -80,6 +85,7 @@ struct xadc_ops {
|
|||
irqreturn_t (*interrupt_handler)(int irq, void *devid);
|
||||
|
||||
unsigned int flags;
|
||||
enum xadc_type type;
|
||||
};
|
||||
|
||||
static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
|
||||
|
|
|
|||
Loading…
Reference in New Issue