mirror of https://gitee.com/openkylin/linux.git
[media] v4l: vsp1: Split display list manager from display list
This clarifies the API and prepares display list support for being used to implement the request API. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
This commit is contained in:
Laurent Pinchart
Mauro Carvalho Chehab
parent
f9df34f8cd
commit
c2dd2513ea
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@ -26,7 +26,6 @@
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struct clk;
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struct device;
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struct vsp1_dl;
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struct vsp1_drm;
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struct vsp1_entity;
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struct vsp1_platform_data;
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@ -37,117 +37,108 @@ struct vsp1_dl_entry {
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} __attribute__((__packed__));
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struct vsp1_dl_list {
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size_t size;
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int reg_count;
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struct list_head list;
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bool in_use;
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struct vsp1_dl_manager *dlm;
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struct vsp1_dl_entry *body;
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dma_addr_t dma;
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};
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/**
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* struct vsp1_dl - Display List manager
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* @vsp1: the VSP1 device
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* @lock: protects the active, queued and pending lists
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* @lists.all: array of all allocate display lists
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* @lists.active: list currently being processed (loaded) by hardware
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* @lists.queued: list queued to the hardware (written to the DL registers)
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* @lists.pending: list waiting to be queued to the hardware
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* @lists.write: list being written to by software
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*/
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struct vsp1_dl {
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struct vsp1_device *vsp1;
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spinlock_t lock;
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size_t size;
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dma_addr_t dma;
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void *mem;
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struct {
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struct vsp1_dl_list all[VSP1_DL_NUM_LISTS];
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struct vsp1_dl_list *active;
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struct vsp1_dl_list *queued;
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struct vsp1_dl_list *pending;
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struct vsp1_dl_list *write;
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} lists;
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int reg_count;
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};
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/* -----------------------------------------------------------------------------
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* Display List Transaction Management
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*/
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static void vsp1_dl_free_list(struct vsp1_dl_list *list)
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static struct vsp1_dl_list *vsp1_dl_list_alloc(struct vsp1_dl_manager *dlm)
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{
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if (!list)
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struct vsp1_dl_list *dl;
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dl = kzalloc(sizeof(*dl), GFP_KERNEL);
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if (!dl)
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return NULL;
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dl->dlm = dlm;
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dl->size = VSP1_DL_BODY_SIZE;
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dl->body = dma_alloc_wc(dlm->vsp1->dev, dl->size, &dl->dma, GFP_KERNEL);
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if (!dl->body) {
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kfree(dl);
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return NULL;
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}
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return dl;
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}
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static void vsp1_dl_list_free(struct vsp1_dl_list *dl)
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{
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dma_free_wc(dl->dlm->vsp1->dev, dl->size, dl->body, dl->dma);
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kfree(dl);
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}
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/**
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* vsp1_dl_list_get - Get a free display list
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* @dlm: The display list manager
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*
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* Get a display list from the pool of free lists and return it.
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*
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* This function must be called without the display list manager lock held.
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*/
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struct vsp1_dl_list *vsp1_dl_list_get(struct vsp1_dl_manager *dlm)
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{
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struct vsp1_dl_list *dl = NULL;
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unsigned long flags;
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spin_lock_irqsave(&dlm->lock, flags);
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if (!list_empty(&dlm->free)) {
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dl = list_first_entry(&dlm->free, struct vsp1_dl_list, list);
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list_del(&dl->list);
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}
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spin_unlock_irqrestore(&dlm->lock, flags);
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return dl;
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}
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/**
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* vsp1_dl_list_put - Release a display list
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* @dl: The display list
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*
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* Release the display list and return it to the pool of free lists.
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*
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* This function must be called with the display list manager lock held.
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*
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* Passing a NULL pointer to this function is safe, in that case no operation
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* will be performed.
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*/
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void vsp1_dl_list_put(struct vsp1_dl_list *dl)
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{
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if (!dl)
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return;
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list->in_use = false;
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dl->reg_count = 0;
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list_add_tail(&dl->list, &dl->dlm->free);
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}
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void vsp1_dl_reset(struct vsp1_dl *dl)
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void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data)
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{
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unsigned int i;
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dl->lists.active = NULL;
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dl->lists.queued = NULL;
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dl->lists.pending = NULL;
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dl->lists.write = NULL;
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for (i = 0; i < ARRAY_SIZE(dl->lists.all); ++i)
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dl->lists.all[i].in_use = false;
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dl->body[dl->reg_count].addr = reg;
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dl->body[dl->reg_count].data = data;
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dl->reg_count++;
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}
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void vsp1_dl_begin(struct vsp1_dl *dl)
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void vsp1_dl_list_commit(struct vsp1_dl_list *dl)
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{
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struct vsp1_dl_list *list = NULL;
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unsigned long flags;
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unsigned int i;
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spin_lock_irqsave(&dl->lock, flags);
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for (i = 0; i < ARRAY_SIZE(dl->lists.all); ++i) {
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if (!dl->lists.all[i].in_use) {
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list = &dl->lists.all[i];
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break;
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}
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}
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if (!list) {
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list = dl->lists.pending;
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dl->lists.pending = NULL;
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}
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spin_unlock_irqrestore(&dl->lock, flags);
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dl->lists.write = list;
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list->in_use = true;
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list->reg_count = 0;
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}
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void vsp1_dl_add(struct vsp1_dl *dl, u32 reg, u32 data)
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{
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struct vsp1_dl_list *list = dl->lists.write;
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list->body[list->reg_count].addr = reg;
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list->body[list->reg_count].data = data;
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list->reg_count++;
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}
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void vsp1_dl_commit(struct vsp1_dl *dl)
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{
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struct vsp1_device *vsp1 = dl->vsp1;
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struct vsp1_dl_list *list;
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struct vsp1_dl_manager *dlm = dl->dlm;
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struct vsp1_device *vsp1 = dlm->vsp1;
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unsigned long flags;
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bool update;
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list = dl->lists.write;
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dl->lists.write = NULL;
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spin_lock_irqsave(&dl->lock, flags);
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spin_lock_irqsave(&dlm->lock, flags);
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/* Once the UPD bit has been set the hardware can start processing the
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* display list at any time and we can't touch the address and size
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@ -156,8 +147,8 @@ void vsp1_dl_commit(struct vsp1_dl *dl)
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*/
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update = !!(vsp1_read(vsp1, VI6_DL_BODY_SIZE) & VI6_DL_BODY_SIZE_UPD);
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if (update) {
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vsp1_dl_free_list(dl->lists.pending);
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dl->lists.pending = list;
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vsp1_dl_list_put(dlm->pending);
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dlm->pending = dl;
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goto done;
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}
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@ -165,42 +156,44 @@ void vsp1_dl_commit(struct vsp1_dl *dl)
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* The UPD bit will be cleared by the device when the display list is
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* processed.
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*/
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vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), list->dma);
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vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), dl->dma);
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vsp1_write(vsp1, VI6_DL_BODY_SIZE, VI6_DL_BODY_SIZE_UPD |
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(list->reg_count * 8));
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(dl->reg_count * 8));
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vsp1_dl_free_list(dl->lists.queued);
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dl->lists.queued = list;
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vsp1_dl_list_put(dlm->queued);
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dlm->queued = dl;
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done:
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spin_unlock_irqrestore(&dl->lock, flags);
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spin_unlock_irqrestore(&dlm->lock, flags);
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}
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/* -----------------------------------------------------------------------------
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* Interrupt Handling
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* Display List Manager
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*/
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void vsp1_dl_irq_display_start(struct vsp1_dl *dl)
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/* Interrupt Handling */
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void vsp1_dlm_irq_display_start(struct vsp1_dl_manager *dlm)
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{
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spin_lock(&dl->lock);
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spin_lock(&dlm->lock);
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/* The display start interrupt signals the end of the display list
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* processing by the device. The active display list, if any, won't be
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* accessed anymore and can be reused.
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*/
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if (dl->lists.active) {
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vsp1_dl_free_list(dl->lists.active);
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dl->lists.active = NULL;
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}
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vsp1_dl_list_put(dlm->active);
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dlm->active = NULL;
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spin_unlock(&dl->lock);
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spin_unlock(&dlm->lock);
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}
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void vsp1_dl_irq_frame_end(struct vsp1_dl *dl)
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void vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm)
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{
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struct vsp1_device *vsp1 = dl->vsp1;
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struct vsp1_device *vsp1 = dlm->vsp1;
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spin_lock(&dl->lock);
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spin_lock(&dlm->lock);
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vsp1_dl_list_put(dlm->active);
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dlm->active = NULL;
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/* The UPD bit set indicates that the commit operation raced with the
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* interrupt and occurred after the frame end event and UPD clear but
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@ -213,35 +206,31 @@ void vsp1_dl_irq_frame_end(struct vsp1_dl *dl)
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/* The device starts processing the queued display list right after the
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* frame end interrupt. The display list thus becomes active.
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*/
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if (dl->lists.queued) {
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WARN_ON(dl->lists.active);
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dl->lists.active = dl->lists.queued;
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dl->lists.queued = NULL;
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if (dlm->queued) {
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dlm->active = dlm->queued;
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dlm->queued = NULL;
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}
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/* Now that the UPD bit has been cleared we can queue the next display
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* list to the hardware if one has been prepared.
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*/
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if (dl->lists.pending) {
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struct vsp1_dl_list *list = dl->lists.pending;
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if (dlm->pending) {
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struct vsp1_dl_list *dl = dlm->pending;
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vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), list->dma);
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vsp1_write(vsp1, VI6_DL_HDR_ADDR(0), dl->dma);
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vsp1_write(vsp1, VI6_DL_BODY_SIZE, VI6_DL_BODY_SIZE_UPD |
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(list->reg_count * 8));
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(dl->reg_count * 8));
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dl->lists.queued = list;
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dl->lists.pending = NULL;
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dlm->queued = dl;
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dlm->pending = NULL;
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}
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done:
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spin_unlock(&dl->lock);
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spin_unlock(&dlm->lock);
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}
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/* -----------------------------------------------------------------------------
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* Hardware Setup
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*/
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void vsp1_dl_setup(struct vsp1_device *vsp1)
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/* Hardware Setup */
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void vsp1_dlm_setup(struct vsp1_device *vsp1)
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{
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u32 ctrl = (256 << VI6_DL_CTRL_AR_WAIT_SHIFT);
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@ -256,46 +245,46 @@ void vsp1_dl_setup(struct vsp1_device *vsp1)
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vsp1_write(vsp1, VI6_DL_SWAP, VI6_DL_SWAP_LWS);
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}
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/* -----------------------------------------------------------------------------
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* Initialization and Cleanup
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*/
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struct vsp1_dl *vsp1_dl_create(struct vsp1_device *vsp1)
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void vsp1_dlm_reset(struct vsp1_dl_manager *dlm)
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{
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vsp1_dl_list_put(dlm->active);
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vsp1_dl_list_put(dlm->queued);
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vsp1_dl_list_put(dlm->pending);
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dlm->active = NULL;
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dlm->queued = NULL;
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dlm->pending = NULL;
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}
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int vsp1_dlm_init(struct vsp1_device *vsp1, struct vsp1_dl_manager *dlm,
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unsigned int prealloc)
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{
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struct vsp1_dl *dl;
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unsigned int i;
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dl = kzalloc(sizeof(*dl), GFP_KERNEL);
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if (!dl)
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return NULL;
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dlm->vsp1 = vsp1;
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spin_lock_init(&dl->lock);
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spin_lock_init(&dlm->lock);
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INIT_LIST_HEAD(&dlm->free);
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dl->vsp1 = vsp1;
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dl->size = VSP1_DL_BODY_SIZE * ARRAY_SIZE(dl->lists.all);
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for (i = 0; i < prealloc; ++i) {
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struct vsp1_dl_list *dl;
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dl->mem = dma_alloc_wc(vsp1->dev, dl->size, &dl->dma,
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GFP_KERNEL);
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if (!dl->mem) {
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kfree(dl);
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return NULL;
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dl = vsp1_dl_list_alloc(dlm);
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if (!dl)
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return -ENOMEM;
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list_add_tail(&dl->list, &dlm->free);
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}
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for (i = 0; i < ARRAY_SIZE(dl->lists.all); ++i) {
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struct vsp1_dl_list *list = &dl->lists.all[i];
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list->size = VSP1_DL_BODY_SIZE;
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list->reg_count = 0;
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list->in_use = false;
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list->dma = dl->dma + VSP1_DL_BODY_SIZE * i;
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list->body = dl->mem + VSP1_DL_BODY_SIZE * i;
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}
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return dl;
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return 0;
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}
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void vsp1_dl_destroy(struct vsp1_dl *dl)
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void vsp1_dlm_cleanup(struct vsp1_dl_manager *dlm)
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{
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dma_free_wc(dl->vsp1->dev, dl->size, dl->mem, dl->dma);
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kfree(dl);
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struct vsp1_dl_list *dl, *next;
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list_for_each_entry_safe(dl, next, &dlm->free, list) {
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list_del(&dl->list);
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vsp1_dl_list_free(dl);
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}
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}
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@ -16,19 +16,39 @@
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#include <linux/types.h>
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struct vsp1_device;
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struct vsp1_dl;
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struct vsp1_dl_list;
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struct vsp1_dl *vsp1_dl_create(struct vsp1_device *vsp1);
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void vsp1_dl_destroy(struct vsp1_dl *dl);
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/**
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* struct vsp1_dl_manager - Display List manager
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* @vsp1: the VSP1 device
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* @lock: protects the active, queued and pending lists
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* @free: array of all free display lists
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* @active: list currently being processed (loaded) by hardware
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* @queued: list queued to the hardware (written to the DL registers)
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* @pending: list waiting to be queued to the hardware
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*/
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struct vsp1_dl_manager {
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struct vsp1_device *vsp1;
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void vsp1_dl_setup(struct vsp1_device *vsp1);
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spinlock_t lock;
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struct list_head free;
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struct vsp1_dl_list *active;
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struct vsp1_dl_list *queued;
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struct vsp1_dl_list *pending;
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};
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void vsp1_dl_reset(struct vsp1_dl *dl);
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void vsp1_dl_begin(struct vsp1_dl *dl);
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void vsp1_dl_add(struct vsp1_dl *dl, u32 reg, u32 data);
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void vsp1_dl_commit(struct vsp1_dl *dl);
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void vsp1_dlm_setup(struct vsp1_device *vsp1);
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void vsp1_dl_irq_display_start(struct vsp1_dl *dl);
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void vsp1_dl_irq_frame_end(struct vsp1_dl *dl);
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int vsp1_dlm_init(struct vsp1_device *vsp1, struct vsp1_dl_manager *dlm,
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unsigned int prealloc);
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void vsp1_dlm_cleanup(struct vsp1_dl_manager *dlm);
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void vsp1_dlm_reset(struct vsp1_dl_manager *dlm);
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void vsp1_dlm_irq_display_start(struct vsp1_dl_manager *dlm);
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void vsp1_dlm_irq_frame_end(struct vsp1_dl_manager *dlm);
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struct vsp1_dl_list *vsp1_dl_list_get(struct vsp1_dl_manager *dlm);
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void vsp1_dl_list_put(struct vsp1_dl_list *dl);
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void vsp1_dl_list_write(struct vsp1_dl_list *dl, u32 reg, u32 data);
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void vsp1_dl_list_commit(struct vsp1_dl_list *dl);
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#endif /* __VSP1_DL_H__ */
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|
|
@ -26,6 +26,18 @@
|
|||
#include "vsp1_pipe.h"
|
||||
#include "vsp1_rwpf.h"
|
||||
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Interrupt Handling
|
||||
*/
|
||||
|
||||
void vsp1_drm_frame_end(struct vsp1_pipeline *pipe)
|
||||
{
|
||||
struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
|
||||
|
||||
vsp1_dlm_irq_frame_end(&vsp1->drm->dlm);
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* DU Driver API
|
||||
*/
|
||||
|
|
@ -89,6 +101,7 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int width,
|
|||
|
||||
pipe->num_inputs = 0;
|
||||
|
||||
vsp1_dlm_reset(&vsp1->drm->dlm);
|
||||
vsp1_device_put(vsp1);
|
||||
|
||||
dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);
|
||||
|
|
@ -96,8 +109,6 @@ int vsp1_du_setup_lif(struct device *dev, unsigned int width,
|
|||
return 0;
|
||||
}
|
||||
|
||||
vsp1_dl_reset(vsp1->drm->dl);
|
||||
|
||||
/* Configure the format at the BRU sinks and propagate it through the
|
||||
* pipeline.
|
||||
*/
|
||||
|
|
@ -217,7 +228,7 @@ void vsp1_du_atomic_begin(struct device *dev)
|
|||
spin_unlock_irqrestore(&pipe->irqlock, flags);
|
||||
|
||||
/* Prepare the display list. */
|
||||
vsp1_dl_begin(vsp1->drm->dl);
|
||||
pipe->dl = vsp1_dl_list_get(&vsp1->drm->dlm);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
|
||||
|
||||
|
|
@ -467,7 +478,8 @@ void vsp1_du_atomic_flush(struct device *dev)
|
|||
}
|
||||
}
|
||||
|
||||
vsp1_dl_commit(vsp1->drm->dl);
|
||||
vsp1_dl_list_commit(pipe->dl);
|
||||
pipe->dl = NULL;
|
||||
|
||||
spin_lock_irqsave(&pipe->irqlock, flags);
|
||||
|
||||
|
|
@ -543,18 +555,20 @@ int vsp1_drm_init(struct vsp1_device *vsp1)
|
|||
{
|
||||
struct vsp1_pipeline *pipe;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
|
||||
if (!vsp1->drm)
|
||||
return -ENOMEM;
|
||||
|
||||
vsp1->drm->dl = vsp1_dl_create(vsp1);
|
||||
if (!vsp1->drm->dl)
|
||||
return -ENOMEM;
|
||||
ret = vsp1_dlm_init(vsp1, &vsp1->drm->dlm, 4);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
pipe = &vsp1->drm->pipe;
|
||||
|
||||
vsp1_pipeline_init(pipe);
|
||||
pipe->frame_end = vsp1_drm_frame_end;
|
||||
|
||||
/* The DRM pipeline is static, add entities manually. */
|
||||
for (i = 0; i < vsp1->info->rpf_count; ++i) {
|
||||
|
|
@ -571,12 +585,10 @@ int vsp1_drm_init(struct vsp1_device *vsp1)
|
|||
pipe->lif = &vsp1->lif->entity;
|
||||
pipe->output = vsp1->wpf[0];
|
||||
|
||||
pipe->dl = vsp1->drm->dl;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void vsp1_drm_cleanup(struct vsp1_device *vsp1)
|
||||
{
|
||||
vsp1_dl_destroy(vsp1->drm->dl);
|
||||
vsp1_dlm_cleanup(&vsp1->drm->dlm);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,26 +13,30 @@
|
|||
#ifndef __VSP1_DRM_H__
|
||||
#define __VSP1_DRM_H__
|
||||
|
||||
#include "vsp1_dl.h"
|
||||
#include "vsp1_pipe.h"
|
||||
|
||||
struct vsp1_dl;
|
||||
|
||||
/**
|
||||
* vsp1_drm - State for the API exposed to the DRM driver
|
||||
* @dl: display list for DRM pipeline operation
|
||||
* @pipe: the VSP1 pipeline used for display
|
||||
* @num_inputs: number of active pipeline inputs at the beginning of an update
|
||||
* @update: the pipeline configuration has been updated
|
||||
* @dlm: display list manager used for DRM operation
|
||||
*/
|
||||
struct vsp1_drm {
|
||||
struct vsp1_dl *dl;
|
||||
struct vsp1_pipeline pipe;
|
||||
unsigned int num_inputs;
|
||||
bool update;
|
||||
struct vsp1_dl_manager dlm;
|
||||
};
|
||||
|
||||
int vsp1_drm_init(struct vsp1_device *vsp1);
|
||||
void vsp1_drm_cleanup(struct vsp1_device *vsp1);
|
||||
int vsp1_drm_create_links(struct vsp1_device *vsp1);
|
||||
|
||||
static inline void vsp1_drm_display_start(struct vsp1_device *vsp1)
|
||||
{
|
||||
vsp1_dlm_irq_display_start(&vsp1->drm->dlm);
|
||||
}
|
||||
|
||||
#endif /* __VSP1_DRM_H__ */
|
||||
|
|
|
|||
|
|
@ -68,14 +68,7 @@ static irqreturn_t vsp1_irq_handler(int irq, void *data)
|
|||
vsp1_write(vsp1, VI6_DISP_IRQ_STA, ~status & VI6_DISP_IRQ_STA_DST);
|
||||
|
||||
if (status & VI6_DISP_IRQ_STA_DST) {
|
||||
struct vsp1_rwpf *wpf = vsp1->wpf[0];
|
||||
struct vsp1_pipeline *pipe;
|
||||
|
||||
if (wpf) {
|
||||
pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity);
|
||||
vsp1_pipeline_display_start(pipe);
|
||||
}
|
||||
|
||||
vsp1_drm_display_start(vsp1);
|
||||
ret = IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
|
@ -462,7 +455,7 @@ static int vsp1_device_init(struct vsp1_device *vsp1)
|
|||
vsp1_write(vsp1, VI6_DPR_HGT_SMPPT, (7 << VI6_DPR_SMPPT_TGW_SHIFT) |
|
||||
(VI6_DPR_NODE_UNUSED << VI6_DPR_SMPPT_PT_SHIFT));
|
||||
|
||||
vsp1_dl_setup(vsp1);
|
||||
vsp1_dlm_setup(vsp1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ void vsp1_mod_write(struct vsp1_entity *e, u32 reg, u32 data)
|
|||
struct vsp1_pipeline *pipe = to_vsp1_pipeline(&e->subdev.entity);
|
||||
|
||||
if (pipe->dl)
|
||||
vsp1_dl_add(pipe->dl, reg, data);
|
||||
vsp1_dl_list_write(pipe->dl, reg, data);
|
||||
else
|
||||
vsp1_write(e->vsp1, reg, data);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -226,7 +226,7 @@ int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
|
|||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
if (pipe->dl) {
|
||||
if (pipe->lif) {
|
||||
/* When using display lists in continuous frame mode the only
|
||||
* way to stop the pipeline is to reset the hardware.
|
||||
*/
|
||||
|
|
@ -271,12 +271,6 @@ bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
|
|||
return pipe->buffers_ready == mask;
|
||||
}
|
||||
|
||||
void vsp1_pipeline_display_start(struct vsp1_pipeline *pipe)
|
||||
{
|
||||
if (pipe->dl)
|
||||
vsp1_dl_irq_display_start(pipe->dl);
|
||||
}
|
||||
|
||||
void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
|
||||
{
|
||||
enum vsp1_pipeline_state state;
|
||||
|
|
@ -285,9 +279,6 @@ void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
|
|||
if (pipe == NULL)
|
||||
return;
|
||||
|
||||
if (pipe->dl)
|
||||
vsp1_dl_irq_frame_end(pipe->dl);
|
||||
|
||||
/* Signal frame end to the pipeline handler. */
|
||||
if (pipe->frame_end)
|
||||
pipe->frame_end(pipe);
|
||||
|
|
@ -299,7 +290,7 @@ void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
|
|||
/* When using display lists in continuous frame mode the pipeline is
|
||||
* automatically restarted by the hardware.
|
||||
*/
|
||||
if (pipe->dl)
|
||||
if (pipe->lif)
|
||||
goto done;
|
||||
|
||||
pipe->state = VSP1_PIPELINE_STOPPED;
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
|
||||
#include <media/media-entity.h>
|
||||
|
||||
struct vsp1_dl;
|
||||
struct vsp1_dl_list;
|
||||
struct vsp1_rwpf;
|
||||
|
||||
/*
|
||||
|
|
@ -100,7 +100,7 @@ struct vsp1_pipeline {
|
|||
|
||||
struct list_head entities;
|
||||
|
||||
struct vsp1_dl *dl;
|
||||
struct vsp1_dl_list *dl;
|
||||
};
|
||||
|
||||
static inline struct vsp1_pipeline *to_vsp1_pipeline(struct media_entity *e)
|
||||
|
|
@ -119,7 +119,6 @@ bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe);
|
|||
int vsp1_pipeline_stop(struct vsp1_pipeline *pipe);
|
||||
bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe);
|
||||
|
||||
void vsp1_pipeline_display_start(struct vsp1_pipeline *pipe);
|
||||
void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe);
|
||||
|
||||
void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
|
||||
|
|
|
|||
Loading…
Reference in New Issue